Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2000-06-28
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S154000
Reexamination Certificate
active
06292388
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the field of integrated circuits (ICs) and pertains in particular to a new memory cell suitable for use in programmable logic devices for configuration control.
BACKGROUND OF THE INVENTION
Arrangements of transistors in ICs to act as storage locations for binary bits (memory cells) are very well known in the art, and several different arrangements are used for different purposes. It is well known, as well, that memory cells have been integrated in many different ways in many kinds of IC devices. One such device is known as a programmable logic array (PLA), wherein memory cells are used to store bit strings that configure the PLA, that is, that program the PLA to one of the many purposes to which it may be applied. By storing different words in different patterns of memory cells in a PLA, the PLA can be configured to operate in a variety of different ways. Many reference books are available with information on both memory cells and PLAs.
In a PLA the characteristics of the memory cells are quite important. For example, the characteristics of the memory cell structure influence the power requirement and time for power up. Further, in operation of a PLA the state of the memory cells is frequently read for a variety of reasons. The characteristics of the cell structure determine the stability of cells during read operations. If a cell is relatively unstable, it may be flipped to the alternate state during a read operation.
In addition to the above, it is often desirable to alter the pattern of memory words stored in the memory cells in the PLA, to change the configuration of the PLA. In this process it is also desirable to reset the memory structure, that is, to drive all memory cells to a “1” condition, or all to a “0” condition, and then to write new data to the cells. The energy required to flip a single cell is vastly multiplied at reset because there are a very large number of memory cells in a state-of-the-art PLA. Flipping all cells results in a large current requirement. Without special design considerations in the memory system, current designs have a requirement that relatively small groups of cells may be written simultaneously.
What is clearly needed is a new and robust memory cell design that is stable for read operations, and at the same time requires a relatively low energy to flip the cell during a write operation. Just such a cell structure and operation is described in enabling detail below.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention a memory system with an operating voltage of Vcc is provided, comprising a memory cell having first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage controlled Vmm line; a passgate transistor connected source to drain from a BIT line to the first inverter output, the passgate having a strength low enough that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch; and circuitry for reducing the voltage of Vmm during a write cycle, so a signal on the BIT line may flip the latch through the passgate. In some embodiments the Vmm node is driven by the output of a NAND gate whose inputs are a WRITE signal and the WORD signal. Also in some embodiments the WORD signal is driven by the output of a NOR gate whose inputs are Address signals.
In some preferred embodiments of the invention there are multiple memory cells defining bits for a binary word, each of the cells structured as the cell of claim
1
, and the WORD line is connected to the gate of a passgate transistor for each of the multiple cells, and the cells also share a common Vmm line powering the cell inverters. There may further be multiple binary words which share common bit lines.
In another aspect of the invention a Programmable Logic Array (PLA) is provided, comprising a memory system with an operating voltage of Vcc, the memory system further comprising a memory cell having first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage controlled Vmm line; a passgate transistor connected source to drain from a BIT line to the first inverter output, the passgate having a strength low enough that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch; and circuitry for reducing the voltage of Vmm. The voltage on Vmm is reduced to a value substantially below Vcc during a write cycle to enable a signal on the BIT line to flip the latch through the passgate.
In some embodiments of the PLA the Vmm node is driven by the output of a NAND gate whose inputs are a WRITE signal and the WORD signal, and the WORD signal is driven by the output of a NOR gate whose inputs are Address signals.
In some embodiments the PLA may comprise multiple memory cells defining bits for a binary word, each of the cells structured as the cell of claim
1
, and the WORD line is connected to the gate of a passgate transistor for each of the multiple cells for a single word, which also share a common Vmm line powering the inverters. There may in addition be multiple binary words which share common bit lines.
In another aspect of the invention a method for reducing the energy required to write to a memory cell with nodes energized by a power line Vmm is provided, comprising the steps of (a) connecting Vmm to the nodes of the memory cell through circuitry enabled to lower the voltage on Vmm while a Write signal is asserted; and (b) energizing a passgate to one of the nodes of the cell for a period of time common to the period of time that voltage is lowered on Vmm.
In embodiments of the invention taught in enabling detail below, for the first time a memory cell is provided that is more stable to accidental changing of state than is the case with conventional memory cells, and that also minimizes the energy required to write to the cells, so, in many applications, many more bits may be written or reset at the same time than has been possible with devices of the prior art.
REFERENCES:
patent: 5831896 (1998-11-01), Lattimore et al.
Adaptive Silicon, Inc.
Boys Donald R.
Central Coast Patent Agency Inc.
Nelms David
Tran M.
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