Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-05-29
2007-05-29
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C711S100000, C711S150000, C711S151000, C711S157000, C711S173000, C365S230010, C365S230030, C365S189011, C365S189020, C365S189040
Reexamination Certificate
active
10970182
ABSTRACT:
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum. Here A is the average delay of the symbols through the interleaver. The address generation circuit (with simple adders and registers) works for variable P,D,m. This is achieved by decomposing the (P,D,m) interleaver into a concatenation of a multiplexed interleaver (implemented with A+1 memory locations), followed by a block interleaver (implemented with 2P memory locations). In many applications, these 2P memory locations can be treated as part of the memory for controlling the data flow of the system.
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Forney, G. D., “Burst-Correcting Codes for the Classic Bursty Channel,”IEEE Transactions on Communication Technology, IEEE Inc. New York, US, vol.19, No. 5, Oct. 1, 1971, pp. 772-781.
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Brady W. James
Li Zhuo H.
Shah Sanjiv
Shaw Steven A.
Telecky , Jr. Frederick J.
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