Efficient 4:1 multiplexer for programmable chips

Details Efficient 4:1 multiplexer for programmable chips Efficient 4:1 multiplexer for programmable chips

2008-04-15

2008-04-15

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C327S407000

Reexamination Certificate

active

10997792

ABSTRACT:
Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table (LUT). A load logic input line associated with a LUT having limited input lines is used to augment the number of input lines that can be handled by a particular LUT. A reset logic input line associated with a LUT is further used to augment the number of input lines. Load logic, reset logic, and a LUT having four input lines can be used to implement a 4:1 multiplexer having seven input lines including four data and three control lines.

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