Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-16
2011-08-16
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
08001331
ABSTRACT:
A processing system1including a memory10and a cache memory4is provided with a page status unit40for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.
REFERENCES:
patent: 5893136 (1999-04-01), Stolt et al.
patent: 6523092 (2003-02-01), Fanning
patent: 7020751 (2006-03-01), Kershaw
patent: 2007/096572 (2007-08-01), None
Lin, W. et al., “Reducing DRAM Latencies with an Integrated Memory Hierarchy Design”, IEEE Computer Society, 12 pages, (2001).
Rixner, S. et al., “Memory Access Scheduling”, Appears in ISCA-27, pp. 1-11, (2000).
Biles Stuart David
Mace Timothy Charles
Paver Nigel Charles
Sudanthi Chander
ARM Limited
Nixon & Vanderhye P.C.
Peugh Brian R
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