Effective-to-real address cache managing apparatus and method

Details Effective-to-real address cache managing apparatus and method Effective-to-real address cache managing apparatus and method

1997-11-10

2000-02-01

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711210, 711144, G06F 1210

Patent

active

060214813

ABSTRACT:
An effective-to-real address translation cache management apparatus and method utilizes an effective-to-real address translation cache segment register latch having a bit corresponding to each of the segment registers. When a segment register is utilized to perform an effective-to-real address translation, which is stored in the effective-to-real address translation cache, the corresponding bit in the effective-to-real address translation cache segment register latch is set. In this way, a record is kept of which segment registers are currently mapped in the effective-to-real address translation cache. When a move to segment register instruction alters the content of a segment register, then the effective-to-real address translation cache segment register latch is examined to determine if that segment register has been mapped in the effective-to-real address translation cache. If so, then an effective-to-real address translation cache invalidation latch is set. Otherwise, the move to segment register has no effect on the effective-to-real address translation cache. When a context synchronizing event occurs, the effective-to-real address translation cache invalidation latch is examined to determine whether or not to invalidate the effective-to-real address translation cache. In this way, the frequency of effective-to-real address translation cache invalidation may be reduced thereby increasing processor efficiency.

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