Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-24
2004-01-20
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06680239
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to an isolation process used in semiconductor manufacturing and, more particularly, to a method of shallow trench isolation used to isolate adjacent components in sub-micron devices in the fabrication of integrated circuits.
(2) Description of Prior Art
Semiconductor fabrication often employs shallow trench isolation (STI) to provide electrical isolation between adjacent components. Typically, a narrow trench is isotropically etched and filled with a dielectric such as silicon oxide to provide the isolation. As device packing density increases, STI becomes an inevitable feature of the integrated circuit. In deep sub-micron integration STI with higher aspect ratios (height/width) are required.
Using prior techniques, deep and narrow trenches are difficult to etch. Several undesirable effects may arise from devices employing high aspect ratio STI. These include damage to the substrate due to excessive etching and severe microloading effects between dense and open trenches. Additionally, problems may result from incomplete clearing of etch by-product residue at the bottom of narrow trenches.
Other approaches to improve isolation exist. U.S. Pat. No. 5,094,972 to Pierce et al. teaches a method of planarizing an integrated circuit with recessed isolation regions. Boron is implanted at an angle along trench sidewalls to form a channel stop isolation region. Unfortunately, this approach severely limits future scaling of device dimensions. Since boron implantation is only used for narrow trenches, additional masking steps are required to protect wider trenches. U.S. Pat. No. 5,401,998 to Chiu et al teaches a method where angled trenches are formed and then implanted with boron. The trenches are then filled with oxide. The boron prevents inversion of the sidewalls thus avoiding parasitic leakage between n-type source and drain regions. U.S. Pat. No. 5,877,048 to Wu teaches a method where an oxygen implant is used to form buried isolation regions in the substrate. Active devices are then built on top of the oxygen implanted isolation regions. U.S. Pat. No. 5,712,186 to Thakur et al teaches a method where oxygen is implanted below the surface of a field oxide. Thermal oxidation is then used to grow oxide above the implanted oxygen forming a deeper isolation region. This invention requires high-energy ion implantation generating undesirable defects that may result in leakage paths. Thermal oxidation suffers from many problems. It requires high temperature processing techniques not compatible with current technology. In addition, thermal oxide suffers a lack of adequate oxide depth resulting in poor isolation. Thermal oxide grows poorly in narrow trenches and results in a surface topology requiring additional planarization U.S. Pat. No. 5,943,579 to Tran teaches a method where a field implantation under the field oxide (FOX) in non-active areas forms isolation regions.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a process that allows the formation of narrower and deeper trench isolation regions.
Another object of the present invention is to provide a method that avoids substrate damage due to excessive etching.
Another object of the present invention is to provide a method that avoids severe microloading effects between dense and open trenches.
Yet another object of the present invention is to provide a method that yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench.
These objects are achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.
REFERENCES:
patent: 5094972 (1992-03-01), Pierce et al.
patent: 5401998 (1995-03-01), Chiu et al.
patent: 5643822 (1997-07-01), Furukawa et al.
patent: 5712186 (1998-01-01), Thakur et al.
patent: 5783476 (1998-07-01), Arnold
patent: 5877048 (1999-03-01), Wu
patent: 5904540 (1999-05-01), Sheng et al.
patent: 5943579 (1999-08-01), Tran
patent: 5989978 (1999-11-01), Peidous
patent: 6069057 (2000-05-01), Wu
patent: 6093611 (2000-07-01), Gardner et al.
Cha Cher Liang
Chan Lap
Ong Kok Keng
See Alex
Blum David S
Chartered Semiconductor Manufacturing Ltd.
Jr. Carl Whitehead
Pike Rosemary L. S.
Saile George O.
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