Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2006-09-21
2009-12-15
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S233000, C712S236000
Reexamination Certificate
active
07634644
ABSTRACT:
Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.
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Chaudhry Shailender
Jacobson Quinn A.
Tremblay Marc
Alrobaye Idriss N
Chan Eddie P
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Sun Microsystems Inc.
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