Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-03
2004-03-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06701499
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of integrated circuit design, and particularly to the design of integrated circuits employing smooth functions through the use of approximated calculation of smooth functions.
BACKGROUND OF THE INVENTION
Because the complexity of integrated circuits, such as an application specific integrated circuit (ASIC), system on a chip (SOC), general purpose integrated circuits, and the like, is increasing on a daily basis, the design of a circuit has become even more complex. One way of addressing this complexity is to mathematically describe the integrated circuit, so that the design may be instantiated and manipulated in an efficient manner. For instance, an information handling system may be configured by a program of instructions to describe a design of an integrated circuit, and then enable an operator of the information handling system to manipulate the design in an efficient manner. However, if the function, structure and connectivity cannot be described mathematically, then that structure may not be provided in a system in this nature.
For instance, in various integrated circuits, it is necessary to perform calculations of “smooth” functions. Typically, this calculation may only be performed with a limited accuracy, and, in some cases, effective implementations of “f” do not use the algebraic definition of “f” but are based on direct application to “f” general synthesis techniques, like Binary Decision Diagram (BDD) expansion. However, BDDs based on smooth functions may be needlessly complicated, thereby resulting in the waste of integrated circuit resources, which may further increase the cost of design and production of the product.
Therefore, it would be desirable to provide a system and method for design of integrated circuits employing smooth functions through the use of approximated calculation of smooth functions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method for effective approximation of smooth functions. In an aspect of the present invention, a method for approximating a smooth function for implementation in an integrated circuit design includes receiving a function f for computation with an accuracy of m bits by an integrated circuit. The argument x may be represented in a form of a fixed-point number with n binary digits. The function is computed based on an operator with one more output than the accuracy of m bits, so that F′: (x
1
x
2
. . . x
N
)→(f
1
f
2
. . . f
M
f
M+1
). A value of f′ is determined by choosing from one of the at least two numbers f′
1
(x)=2
−M−1
[2
M+1
f(x)] and f′
2
(x)=2
−M−1
[2
M+1
f(x)+1]. The value is chosen based on complexity issues in the construction of a binary decision diagram for use in designing the integrated circuit.
In an additional aspect of the present invention, a system for designing an integrated circuit, the integrated circuit designed to perform smooth functions, includes a memory for storing a program of instructions and a processor communicatively coupled to the memory. The processor is suitable for performing the program of instructions which configures the processor to receive a function f for computation with an accuracy of m bits by an integrated circuit design, with argument x represented in a form of a fixed-point number with n binary digits. The function f is computed based on an operator with one more output than the accuracy of m bits, so that the function is computed as an m+1 digit approximation of the function f. A value of f′ is determined by choosing the value from one of at least two numbers computed as an m+1 digit approximation of the function f, wherein the value is chosen based on complexity issues in the construction of a binary decision diagram for use in designing the integrated circuit.
In a further aspect of the present invention, a method for approximating a smooth function for implementation in an integrated circuit design includes receiving a function f for computation with an accuracy of m bits by an integrated circuit, with argument x represented in a form of a fixed-point number with n binary digits. The function is computed based on an operator with one more output than the accuracy of m bits, so that F′: (x
1
x
2
. . . x
N
) (f
1
f
2
. . . f
M
f
M+1
). A value of f′ is determined for inclusion in a binary decision diagram for the function f, wherein an exact value of f′ is not determined by the function f itself, but chosen from one of the at least two numbers f′
1
(x)=2
−M−1
[2
M+1
f(x)] and f′
2
(x)=2
−M−1
[2
M+1
f(x)+1]. The value is chosen based on complexity issues in the construction of a binary decision diagram for use in designing the integrated circuit. a binary decision diagram based on the chosen values and a netlist is constructed utilizing the created binary decision diagram.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 6212669 (2001-04-01), Jain
patent: 6421815 (2002-07-01), Seawright
patent: 6457162 (2002-09-01), Stanion
patent: 6567959 (2003-05-01), Levin et al.
patent: 2002/0138812 (2002-09-01), Johannsen
Forth et al. (An efficient Heuristic for state encoding Miniminzing the BDD Representations of the Transition Relations of Finite State Machines Jan. 25-28, 2001).*
Ashar et al. (Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams Oct. 14-16, 1991).*
Felt et al. (Dynamic Variable Reordering for BDD Minimization Sep. 20-24, 1993).*
Krohm el al. (The Use of Random Simulation in Formal Verification Oct. 7-9, 1996).
LSI Logic Corporation
Siek Vuthe
Suiter-West PC LLO
Tat Binh C.
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