EEPROM with reduced manufacturing complexity

Details EEPROM with reduced manufacturing complexity EEPROM with reduced manufacturing complexity

2002-12-30

2004-05-11

Tran, Thien F (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S317000, C257S321000

Reexamination Certificate

active

06734491

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to semiconductor devices and, more specifically, to an electrically erasable programmable read-only-memory (EEPROM) that has a reduced area and that is more cost effective to manufacture.
BACKGROUND OF THE INVENTION
As is well known, an EEPROM is a user-modifiable read-only memory that can be erased and reprogrammed repeatedly through the application of higher than normal electrical voltage. In general, EEPROM cells have proven to be a reliable and versatile form of nonvolatile reprogrammable memory.
FIG. 1
illustrates a conventional EEPROM device
100
. The EEPROM device
100
includes a semiconductor substrate
105
having a source implant
110
, a drain implant
115
and an additional EEPROM implant
120
formed therein, wherein the EEPROM implant
120
is employed to connect the drain
115
with a tunneling region
135
. A channel region
125
in the semiconductor substrate
105
is defined between the source implant
110
and EEPROM implant
120
. A first dielectric layer
130
is located at least over the channel region
125
and the EEPROM implant
1
.
20
. The first dielectric layer
130
includes a first thickness pT
1
over the channel region
125
and a second thickness pT
2
over the EEPROM implant
120
, wherein the second thickness pT
2
is substantially less than the first thickness pT
1
. The EEPROM device
100
also includes a floating gate
140
, a second dielectric layer
145
, and a control gate
150
sequentially formed over the first dielectric layer
130
, each conforming to the contour of the first dielectric layer
130
.
Despite the success of EEPROM cells as a reliable and versatile form of nonvolatile reprogrammable memory, conventional EEPROM devices, such as the one illustrated in
FIG. 1
, have their drawbacks. One such drawback regards the typical integration of conventional EEPROM cells into existing complimentary metal oxide semiconductor (CMOS) manufacturing processes. Typically, with continued reference to the EEPROM device
100
shown in
FIG. 1
, the first dielectric layer
130
may be formed simultaneously with the gate oxide of a conventional CMOS and the floating gate
140
may be formed simultaneously with the gate of a conventional CMOS, wherein the conventional CMOS may be a high-voltage CMOS.
However, the integration of the EEPROM manufacturing process into conventional CMOS manufacturing processes requires additional manufacturing steps. For example, this integration requires additional process steps to form the EEPROM implant
120
, the first dielectric layer
130
, the second dielectric layer
145
and the control gate
150
. The additional process steps add significant cost and time in fabricating the devices. Moreover, the additional process steps render acceptable defect density more difficult to achieve. Additional production costs are also incurred when the additional steps can not be easily integrated with existing processes. Faced with ever increasing demands for smaller devices, higher yields at lower cost, and reduced production times, it follows that any additional processing steps are undesirable.
Accordingly, what is needed in the art is an EEPROM or other semiconductor device that does not suffer from the deficiencies found in the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides, in one embodiment, a semiconductor device comprising a semiconductor substrate having source and drain regions located therein and having similar doping profiles, wherein a channel region extends from the source region to the drain region. The semiconductor device also comprises a dielectric layer located over the source and drain regions and having first and second thicknesses wherein the second thickness is substantially less than the first thickness and is partially located over the channel region. The semiconductor device also comprises a gate located over the dielectric layer wherein the. second thickness is located between an end of the gate and one of the source and drain regions.
In another embodiment, the present invention provides a method of manufacturing a semiconductor device, the method comprising implanting source and drain regions having similar doping profiles in a semiconductor substrate, thereby defining a channel region extending from the source region to the drain region. The method also comprises locating a dielectric layer over the source and drain regions, wherein the dielectric layer includes first and second thicknesses. The second thickness is substantially less than the first thickness and is partially located over the channel region. The method also comprises forming a gate over the dielectric layer wherein the second thickness is located between an end of the gate and one of the source and drain regions.
In yet another embodiment, the present invention provides an integrated circuit comprising memory cells and transistors formed at least partially within a semiconductor substrate. The memory cells include source and drain regions located in the semiconductor substrate and have similar doping profiles, wherein a channel region extends from the source region to the drain region. The memory cells also include a dielectric layer located over the source and drain regions and have first and second thicknesses, wherein the second thickness is substantially less than the first thickness and is partially located over the channel region. The memory cells also comprise a gate located over the dielectric layer wherein the second thickness is located between an end of the gate and one of the source and drain regions. The integrated circuit also includes interconnects that connect the transistors and the memory cells to form an operative integrated circuit.
The foregoing has outlined features of the present invention such that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that t they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention.


REFERENCES:
patent: 4794433 (1988-12-01), Kamiya et al.
patent: 5604366 (1997-02-01), Lee
patent: 5965913 (1999-10-01), Yuan et al.
patent: 6037625 (2000-03-01), Matsubara et al.
patent: 6441431 (2002-08-01), Efland et al.
Messmer, Hans-Peter; The Indispensable PC Hardware Book: Your Hardware Questions Answered; Third Edition; Addison Wesley Longman; Essex, England; 1997; pp 514-515.

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