Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1996-03-26
2002-01-01
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S321000, C257S315000, C257S411000, C257S336000
Reexamination Certificate
active
06335549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and in particular, to a semiconductor memory device allowing electrical writing and erasing of information as well as a method of manufacturing the same.
2. Description of the Background Art
As one of nonvolatile semiconductor memory devices, there has been known an EEPROM (Electrically Erasable and Programmable Read Only Memory) in which data can be freely programmed and which allows electrical writing and erasing of information. Although the EEPROM has an advantage that both writing and erasing can be executed electrically, it disadvantageously requires two transistors for each memory cell, and therefore integration to a higher degree is difficult. For this reason, there has been proposed a flash EEPROM including memory cells, each of which is formed of one transistor, and allowing electrical entire chip erasing of written electric information charges, for example, in U.S. Pat. No. 4,868,619.
FIG. 53
is a block diagram showing a general structure of a flash EEPROM in the prior art. Referring to
FIG. 53
, the flash EEPROM includes a memory cell matrix
100
, an X-address decoder
200
, a Y-gate sense amplifier
300
, a Y-address decoder
400
, an address buffer
500
, an I/O (input/output) buffer
600
and a control logic
700
.
The memory cell matrix
100
includes a plurality of memory cells arranged in rows and columns. The X-address decoder
200
and Y-gate sense amplifier
300
are connected to the memory cell matrix
100
for selecting the rows and columns thereof. The Y-address decoder
400
is connected to the Y-gate sense amplifier
300
for applying selection information of column thereto. The address buffer
500
is connected to the X-address decoder
200
and Y-address decoder
400
, and temporarily stores the address information.
The Y-gate sense amplifier
300
is connected to the I/O buffer
600
for temporarily storing I/O data. The control logic
700
is connected to the address buffer
500
and I/O buffer
600
for controlling an operation of the flash EEPROM. The control logic
700
carries out the control based on a chip enable signal (/CE), an output enable signal (/OE) and a program signal (/PGM).
FIG. 54
is an equivalent circuit diagram showing a schematic structure of the memory cell matrix
100
shown in FIG.
53
. Referring to
FIG. 54
, the memory cell matrix
100
includes a plurality of word lines WL
1
, WL
2
, . . . WL
1
extending in a row direction and a plurality of bit lines BL
1
, BL
2
, . . . , BL
1
extending in a column direction and perpendicularly crossing the word lines. At crossings of the word lines and bit lines, there are disposed memory transistors Q
11
, Q
12
, . . . Q
11
each having a floating gate electrode, respectively. Each memory transistor has a drain connected to the corresponding bit line, and a control gate electrode connected to the corresponding word line. A source of each memory transistor is connected to corresponding one of the source lines SL
1
, SL
2
. . . , SL
1
, which are connected to source lines S
1
and S
2
disposed at opposite sides.
FIG. 55
is a schematic plan showing a flash EEPROM of a stack gate type in the prior art.
FIG. 56
is a cross section taken along line A—A in FIG.
55
. Referring to
FIGS. 55 and 56
, a structure of the flash EEPROM in the prior art will be described below.
Referring to
FIG. 55
, control gate electrodes
137
are mutually connected to form word lines extending in a lateral direction (row direction). Bit lines
139
extend perpendicularly to the word lines
137
. Each bit line
139
connects drain diffusion regions
132
, which are aligned in a longitudinal direction (column direction), to each other. The bit lines
139
are electrically connected to the drain diffusion regions
132
through drain contacts
140
. Referring to
FIG. 56
, the bit line
139
extends over a smooth coat film
141
. Referring to
FIG. 55
again, source diffusion regions
133
extend along the word lines
137
and are formed in regions surrounded by the word lines
137
and element isolating oxide films
130
. Each drain diffusion region
132
is formed in a region surrounded by the word line
137
and element isolating oxide film
130
.
Referring to
FIG. 56
, at a main surface of a P-type silicon substrate
131
, there are formed the drain diffusion regions
132
and source diffusion regions
133
at opposite sides of channel regions with predetermined spaces between each other. On the channel regions, there are formed floating gate electrodes
135
with a thin oxide film
134
of about 100Å in thickness therebetween. The control gate
137
is formed on each floating gate electrode
135
with an interlayer insulating film
136
therebetween for electrically isolating them from each other. The floating gate electrode
135
and control gate electrode
137
are formed of polysilicon layers. A thermal oxide film
138
is formed by thermal oxidation of surfaces of the P-type silicon substrate
131
as well as floating gate electrode
135
and control gate electrode
137
made of polysilicon layers. The floating gate electrode
135
and control gate electrode
137
are covered with the smooth coat film
141
formed of an oxide film or the like.
An operation of the flash EEPROM will be described below with reference to FIG.
56
.
In a writing operation, a voltage V
D1
of about 6 to 8V is applied to the drain diffusion region
132
, and a voltage V
G1
of about 10 to 15V is applied to the control gate electrode
137
. Thereby, electrons (holes) are accelerated by an electric field near the drain diffusion region
132
and obtain a high energy. The channel hot electrons (holes) which have obtained the high energy are attracted and injected into the floating gate electrode
135
by the electric field which is caused by the voltage V
G1
applied to the control gate electrode
137
. This is called channel hot electron (hole) injection. The channel hot electrons having the high energy impinge against lattices of silicon to generate electron hole pairs. The electrons (holes) thus generated are attracted and injected into the floating gate electrode
135
by the electric field which is caused by the voltage V
G1
applied to the control gate electrode
137
. This is called drain avalanche hot carrier injection. If electrons are accumulated in the floating gate electrode
135
by the channel hot electron injection and drain avalanche hot carrier injection, a threshold voltage V
th
of the control gate transistor increases. The state where the threshold voltage V
th
is higher than a predetermined value is a programmed state and is also referred to as a state of “0”.
In an erasing operation, a voltage V
s
of about 10 to 12 V is applied to the source diffusion region
133
. The control gate electrode
137
is maintained at the ground voltage, and the drain diffusion region
133
is maintained at the floating state. The electric field generated by the voltage V
s
applied to the source diffusion region
133
causes the electrons in the floating gate electrode
135
to pass through the thin oxide film
134
by virtue of an F-N (Fowler-Nordheim) tunneling phenomenon. Owing to the removal of electrons in the floating gate electrode
135
in this manner, the threshold voltage V
th
of the control gate transistor decreases. This state where the threshold voltage V
th
is lower than the predetermined value is an erased state, and is also referred to as a state of “1”. Since the sources of transistors are mutually connected as shown in
FIG. 55
, entire chip erasing of all the memory cells is carried out by this erasing operation.
In reading operation, a voltage V
G2
of about 5 V is applied to the control gate electrode
137
, and a voltage V
D2
of about 1 to 2 V is applied to the drain diffusion region
132
. In this operation, the determination of “1” or “0” described above is carried out based on whether a current flows through the channel region o
Kusunoki Shigeru
Oda Hidekazu
Clark Jhihan B
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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