EEPROM with bit lines below word lines

Details EEPROM with bit lines below word lines EEPROM with bit lines below word lines

1997-09-16

1999-05-04

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, 36518511, 36518513, H01L 29788, G11C 1134

Patent

active

059006617

ABSTRACT:
In a semiconductor device and a manufacturing method therefor, in a nonvolatile semiconductor memory such as an EEPROM having a floating gate, bit lines are formed under word lines to easily and properly realize bit contact, and a memory cell portion and a peripheral circuit portion are manufactured with good uniformity. In the memory cell portion of this nonvolatile semiconductor memory, a polysilicon film is patterned to form a gate counterelectrode and the bit lines substantially at the same level. The gate counterelectrode opposes a floating gate and is capacitively coupled to the floating gate with a dielectric film intervened therebetween on a field oxide film which is an element isolation structure. The word lines extend on an insulating film formed on the bit lines to cross the bit lines and are electrically connected to lower counterelectrodes. Therefore, the bit lines substantially exist under the word lines. The floating gate of the memory cell portion and the gate of the peripheral circuit portion, or the gate counterelectrode and the bit lines of the memory cell portion and the wiring layer of the peripheral circuit portion are simultaneously formed.

REFERENCES:
patent: 4760554 (1988-07-01), Schreck
patent: 5399891 (1995-03-01), Yiu
patent: 5641989 (1997-06-01), Tomioka
patent: 5708285 (1998-01-01), Otani

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