EEPROM type non-volatile memory cell and corresponding...

Details EEPROM type non-volatile memory cell and corresponding... EEPROM type non-volatile memory cell and corresponding...

2000-10-06

2003-06-10

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000

Reexamination Certificate

active

06576950

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a non-volatile memory cell with a single level of polysilicon, in particular of the EEPROM type, and to a method for production of this cell.
BACKGROUND OF THE INVENTION
As is known, the semiconductors market is, with increasing urgency, requiring memory devices which are embedded in other electronic devices, for example advanced-logic devices such as microprocessors. In this type of application, it is necessary firstly to guarantee the functionality and reliability of the memory device, and secondly to keep unchanged as far as possible the performance of the advanced-logic device on the technological platform, and the macro-cell libraries on which the manufacturing methods of the incorporated devices are founded and based. These methods additionally require reduction as far as possible of the method steps which are in addition to those commonly used for production of the advanced-logic devices. In order to achieve this, it is therefore necessary to have memory cells which are highly compatible with the production methods for the said advanced-logic devices, with consequent lower production costs; the circuitry which makes the cells function must also be more efficient and simple.
At present, for this purpose, inter alia, memory cells with a single level of polysilicon are used.
In addition, when it is necessary for the memory cell to be erased per byte, EEPROM type cells are used.
FIGS. 1
,
2
and
3
show in detail an EEPROM type memory cell
2
with a single level of polysilicon included in a memory device
1
, comprising a substrate
3
of semiconductor material with a first type of conductivity, and in particular P.
The memory cell
2
comprises a sensing transistor
20
and a select transistor
21
, which are disposed in series with one another. The sensing transistor
20
is formed in the substrate
3
at a first active region
30
and a second active region
31
, which extend parallel to one another, and are isolated from one another by a field oxide portion
10
a
; field oxide portions
10
b
and
10
c
isolate the first and the second active regions
30
,
31
from adjacent active regions, not shown. The select transistor
21
is formed in the substrate
3
at the second active region
31
. In detail, the sensing transistor
20
comprises a diffuse control gate region
6
, which has a second type of conductivity, and in particular N, formed in the first active region
30
; memory source region
4
and memory drain region
5
, of type N, formed in the second active region
31
; a region of continuity
12
, formed in the second active region
31
, laterally relative to, and partially superimposed on, the memory drain region
5
; and a polycrystalline silicon floating gate region
9
, which extends above the substrate
3
, transversely relative to the first and second active regions
30
,
31
.
The floating gate region
9
is formed from a rectangular portion
9
a
, which extends above the first active region
30
, from a first elongate portion
9
b
and from a second elongate portion
9
c
; the two elongate portions
9
b
,
9
c
extend from the rectangular portion
9
a
above the field oxide portion
10
a
and the second active region
31
. Above the second active region
31
, the first elongate portion
9
b
is superimposed on a first channel region
40
, which is delimited by the memory source region
4
and memory drain region
5
; the second elongate portion
9
c
is superimposed on the continuity region
12
.
The floating gate region
9
is isolated from the substrate
3
by means of a gate oxide region
7
, with the exception of an area above the continuity region
12
, and below the second elongate portion
9
c
, where a thinner, tunnel oxide region
8
is present.
In turn, the select transistor
21
comprises a selection source region
14
, a selection drain region
15
, and a gate region
19
. The selection source region
14
, which in this case is of type N, is formed in the second active region
31
, on the side of the second elongate portion
9
c
of the floating gate region
9
, opposite the memory drain region
5
; the selection source region
14
is partially superimposed on the continuity region
12
of the sensing transistor
20
. The selection drain region
15
, of type N, is also formed in the second active region
31
, and is spaced laterally from the selection source region
14
, such as to delimit a second channel region
41
. The polycrystalline silicon gate region
19
extends transversely relative to the second active region
31
, above the second channel region
41
, and is isolated from the substrate
3
by means of the gate oxide region
7
.
FIGS. 4
to
9
show in succession some steps of the method for production of the memory cell
2
.
In greater detail, starting from the substrate
3
, after the field oxide portions
10
a
,
10
b
,
10
c
have been grown (FIG.
4
), a layer of photo-sensitive material is deposited, in order to form a capacitor mask
50
, which leaves bare the first active region
30
and the part of the second active region
31
in which the continuity region
12
is to be produced. Then, using the capacitor mask
50
, there takes place in succession implantation and diffusion of a doping material, which is typically arsenic or phosphorous, such as to form the diffuse control gate region
6
and the continuity region
12
(
FIGS. 5
a
,
5
b
). The capacitor mask
50
is then removed.
The gate oxide region
7
is then grown on the first and on the second active regions
30
,
31
(
FIGS. 6
a
,
6
b
). There is then deposited a layer of photo-sensitive material, in order to form a tunnel mask
51
, which leaves the second active region
31
bare at the continuity region
12
. After removal of the gate oxide region
7
, in the part which is left bare (
FIGS. 7
a
,
7
b
) the tunnel oxide region
8
is formed (
FIGS. 8
a
,
8
b
).
A polycrystalline silicon layer is then deposited and removed selectively, in order to define simultaneously the floating gate region
9
of the sensing transistor
20
and the gate region
19
of the select transistor
21
(
FIGS. 9
a
,
9
b
).
The method then continues with formation of the memory source region
4
and memory drain region
5
of the sensing transistor
20
, and of the regions of selection source
14
and selection drain
15
of the select transistor
21
(FIGS.
1
-
3
).
Although it is advantageous in various respects, the known memory cell has the disadvantages that it is not highly compatible with the new methods for production of the advanced-logic devices, in which the memory device
1
is incorporated, and it requires complex circuitry in order to function, and is thus costly to produce. In particular, during programming, it is necessary to generate and transfer a high voltage (for example of up to 9 V) to the continuity region
12
, which involves considerable difficulties.
SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a non-volatile memory cell with a single level of polysilicon. The memory cell includes a substrate of semiconductor material, a select transistor, and a sensing transistor. The substrate has a first type of conductivity and includes first and second active regions adjacent to each other. The select transistor is disposed in series relative to the sensing transistor and has selection conduction regions that are formed in the second active region. The sensing transistor includes a control gate region which has a second type of conductivity, formed in the first active region of the substrate, and a floating gate region. The floating gate region extends above the substrate, transversely relative to the first and second active regions. The control, gate region includes a triple-well structure. The triple-well structure includes a first isolating region, which has the second type of conductivity and is formed in the first active region; and a first isolated region, which has the first type of conductivity, and is enclosed below and laterally by first isolating region, the first isolated re

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