EEPROM memory device having a sidewall spacer floating gate elec

Details EEPROM memory device having a sidewall spacer floating gate elec EEPROM memory device having a sidewall spacer floating gate elec

1994-05-02

1995-06-06

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257321, 365185, H01L 29788, H01L 218247

Patent

active

054225043

ABSTRACT:
An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (22) from the source region (12). The control gate electrode (20) overlies a third channel region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

REFERENCES:
patent: 5020030 (1991-05-01), Huber
patent: 5051793 (1991-09-01), Wang
patent: 5063172 (1991-11-01), Manley
patent: 5194925 (1993-03-01), Ajika et al.
patent: 5225362 (1993-07-01), Bergemont
patent: 5338952 (1994-08-01), Yamauchi
Yamauchi, et al., "A 5V-Only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Application", IEEE Sep. 1991, pp. 319-322.

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