Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-06-09
2001-08-28
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189020
Reexamination Certificate
active
06282130
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory chips and, more particularly, to the external connections of electrically erasable and programmable read-only-memory (EEPROM) and flash EEPROM chips.
2. Background Information
A non-volatile memory system such as a Flash EEPROM consists of a number of memory chips. Each chip includes an array of memory cells and their associated peripheral circuitry which is externally connected through a set of pinouts. Command, address, and data information is communicated to the memory thorough these pinouts. Additionally, in EEPROM and Flash memories, there are usually a set of pins for connection to off-chip charge storage.
The voltage needed to program and erase an EEPROM cell is normally higher than normal operating voltage needed to read the memory. To generate the higher voltage, V
pp
, a high voltage generating circuit is used. This high voltage generating circuit is a DC to DC voltage converter usually consisting of some form of charge pump connected to a set of capacitors, where, starting from the standard logic level V
dd
, the voltage on these capacitors is increased from one stage to the next until the voltage V
pp
is reached. In memory systems, the charge pump of a single chip is often used to supply some or all of the other chips in the system. Thus the capacitors must supply not just V
pp
, but most do so with a sufficient programming current. Although most of the high voltage generating circuit is commonly placed on the memory chip, the relatively large charge storage devices are not since these capacitors are not easily implemented as part of the memory chip. Consequently, a number of the pinouts on the chip must be devoted to connecting the off-chip charge storage to the rest of the power generation circuit on the chip, such as is described in U.S. Pat. No. 5,508,971 entitled “Programmable Power Generation Circuit for Flash EEPROM Memory Systems”, and issued to Cernea et al., which is hereby incorporated herein by this reference.
The incorporation of a number of chips are usually into a single memory system is described in U.S. Pat. No. 5,430,859 entitled “Solid State Memory System Including Plural Memory Chips and a Serialized Bus”, and issued to Norman et al., which is hereby incorporated herein by this reference. When data is fed into the system, the address needs to specify the which chip within the system as well as the particular location within the addressed chip. For instance, if the data is fed in by a serial signal a first cycle may indicate the chip to which it is going by a chip address with the array address following in later cycles. The chip then compares this chip address with its own location in order to decide whether it is the addressed chip. To do this, however, requires the chip to know its own address in the device. As the individual chips will likely all be the same, this address is normally specified by how the chip is connected to the system through use of a set of device select pins. These are a subset of the pinouts that, through their connections to the device, inform an individual chip of its address in the system.
As the demand for increased capacity and increased speed in non-volatile memories has grown, so has the demand on the number chip pins. Increasing the number of memory chips per module of a memory system means that a chip needs more device select pins: for example, while four chip select pins uniquely specify a particular chip in a 16-chip module, a 64-chip module requires six such pins. To transfer data more quickly, data is moved in larger units. Although data may be entered serially, this may not be bit-wide serially: for example, data may be programmed or read into the memory cells in a chunk of several bytes at a time in order to transfer this data to or from the cell array faster. To get this chunk of data on or off the chip, it may be moved serially, but in, say, byte-wide serial transfer so that eight pins are required for a serial input or output. These sorts of improvements are described in more detail in copending U.S. patent application Ser. No. 09/505,555, filed Feb. 17, 2000, by Kevin M. Conley, John S. Mangan, and Jeffery G. Craig, entitled “Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks” which is hereby incorporated herein by this reference.
At the same time more pins are required for data transfer and chip identification, there are many reasons why it is preferable to have fewer pins on a chip. One is just a question of the available space around the perimeter of a chip. Fewer pinouts on a memory device results in a smaller device and, consequently, lower device cost. Additionally, pin number, arrangement, and size are often standardized into a, say, 28 pin package so that it is often impractical to change this with each incremental change in chip technology. Also, as a general rule, fewer pins result in lower costs and greater system reliability.
SUMMARY OF THE PRESENT INVENTION
The present invention reduces the demand on the number of pins of an EEPROM memory chip or flash EEPROM chip by multiplexing a subset of the pins between the high voltage generator circuit of the chip and the chip select circuit. When the chip receives an enable signal, the subset of pins are connected to the chip's charge pump circuit allowing it to be connected to an external set of capacitors through these pins. When the enable signal is de-asserted, the subset of pins are connected to the chip select circuit. When the chip is part of an array of chips, this allows this subset of pins to be used to assign a chip address for determining the chips position in the array.
When a number of chips are placed in an array, one (or more) of the chips supplies the other chips in the array with the high voltage and current needed for erasing and programming. To be able to do this, this chip is enabled and connected through the subset of pins to the external capacitors. The other chips are not enabled and use the subset of pins to determine their array address. As the enabled chip (or chips) can not have its address specified in this way, it is placed in a predetermined location within the array and this predetermined address is supplied to the chip select circuit in response to the enable signal.
Additional objects, advantages, and features of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5430859 (1995-07-01), Norman et al.
patent: 5436587 (1995-07-01), Cernea
patent: 5508971 (1996-04-01), Cernea et al.
patent: 5652870 (1997-07-01), Yamasaki et al.
patent: 5724009 (1998-03-01), Collins et al.
patent: 5787299 (1998-07-01), Ostler et al.
patent: 5999480 (1999-12-01), Ong et al.
patent: 2632110A (1989-12-01), None
Cernea Raul-Adrian
Mehrotra Sanjay
Quader Khandker N.
Phan Trong
SanDisk Corporation
Skjerven Morrill & MacPherson LLP
Tran M.
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