EEPROM memory cells matrix with double polysilicon level and rel

Details EEPROM memory cells matrix with double polysilicon level and rel EEPROM memory cells matrix with double polysilicon level and rel

1996-02-26

1999-04-13

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257317, 257321, H01L 2976, H01L 29788

Patent

active

058941460

ABSTRACT:
A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor of the floating gate type which includes two layers of polysilicon superposed on each other and separated by an intervening layer of a dielectric material, and a selection transistor having a gate which comprises a first layer of polysilicon. The gates of the selection transistors in one row of said matrix are connected electrically together by a selection line comprising a second layer of polysilicon overlying the first layer. The intermediate layer of dielectric material is also partly interposed between the first and second layers of polysilicon such that the two layers are in contact at at least one zone of said selection line. Preferably, the contact zone is formed over field oxide regions and is away from the edges of the selection line. The matrix can advantageously be fabricated by a process of the self-aligned type, without making the process any more complicated.

REFERENCES:
patent: 4766088 (1988-08-01), Kono et al.
patent: 5326999 (1994-07-01), Kim et al.
patent: 5472892 (1995-12-01), Gwen et al.
Patent Abstracts of Japan, vol. 16 No. 521 (E-1285), 27 Oct. 1992 & JP-A-04 196175 (Fujitsu Ltd.).
Patent Abstracts of Japan, vol. 13 No. 459 (E-832), 17 Oct. 1989 & JP-A-01 179369 (Toshiba Corp.).

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