EEPROM memory cell with first-dopant-type control gate...

Details EEPROM memory cell with first-dopant-type control gate... EEPROM memory cell with first-dopant-type control gate...

2008-09-18

2010-11-16

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185100

Reexamination Certificate

active

07835184

ABSTRACT:
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

REFERENCES:
patent: 6326663 (2001-12-01), Li
patent: 7002865 (2006-02-01), Agata et al.
patent: 7573749 (2009-08-01), Diorio
patent: 2005/0030827 (2005-02-01), Gilliland et al.
patent: 2007/0070707 (2007-03-01), Yamamoto
patent: 2007/0247914 (2007-10-01), Fang

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