Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reissue Patent
1995-01-23
2001-08-07
Shingleton, Michael B (Department: 2817)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S321000, C365S185040
Reissue Patent
active
RE037308
ABSTRACT:
DESCRIPTION
The present invention relates to an EEPROM memory cell with a single level of polysilicon which can be programmed and erased bit by bit.
There are several references in the literature pertaining to EEPROM cells with a single level of polysilicon which are programmed and erased by Fowler-Nordheim tunneling through a thin oxide or tunnel oxide, utilizing the capacitive couplings between the control gate, the floating gate and the semiconductor substrate.
These cells comprise a selection transistor, a detection transistor and a tunnel condensor. The tunnel condenser is formed by a thin oxide zone with implantation of n
−
phosphorous partially superimposed on the drain diffusion of the detection transistor. A single layer of polysilicon forms the gate of the selection transistor. Separately from the gate of the selection transistor, the single layer of polysilicon forms, in a single piece, (1) an armature of the tunnel condenser, (2) the floating gate of the detection transistor, and (3) an armature of a coupling condenser of the control gate formed with an n
+
diffusion.
Despite the benefit represented by the simplicity of the fabrication process resulting from the use of an n
+
diffusion as the control gate, these known cells have the drawback of being writable by bit but erasable by line (writing being equivalent to the ejection of electrons from the floating gate and erasing being equivalent to the injection of electrons to said floating gate). This is due to the fact that the n
+
diffusion of the control gate is common to all the cells of a given memory line so that the cancellation order, represented by a high level of voltage applied to said n+ diffusion, is automatically and unavoidably extended to all the cells which have the n
+
diffusion in common, i.e. to all the cells of a given line.
Considering this state of the art, the object of the present invention is to accomplish an EEPROM memory cell with a single level of polysilicon which would be both writable and erasable by individual bits.
In accordance with the invention, the above object is achieved by an EEPROM memory cell comprising: a selection transistor, a detection transistor with a floating gate and a control gate, and a tunnel condenser. A thin oxide zone is formed using a single layer of polysilicon for the gate of the selection transistor, the floating gate of the detection transistor and the tunnel condenser and an n
+
diffusion is formed for the control gate. The n
+
diffusion is closed and isolated from that of the other cells of the same memory.
In this manner, the programming sequence applied distinctly to the n
+
diffusion of each individual cell allows a bit-by-bit ERASE operation. Writing is similarly possible bit by bit, performed in the conventional manner by raising the level of the gate of the selection transistor of an entire memory line with the drain contacts to ground (or floating) for all the columns except that of the selected cell.
REFERENCES:
patent: 4019197 (1977-04-01), Lohstroh et al.
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patent: 4417264 (1983-11-01), Angle
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patent: 4531203 (1985-07-01), Masuoka et al.
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patent: 4616245 (1986-10-01), Topich et al.
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patent: 0035160 (1981-09-01), None
patent: 0054355 (1982-06-01), None
patent: 0092488 (1982-06-01), None
Hsieh et al., “Electrically Alterable Memory Cell with Independent Erase Input”, IBM Technical Disclosure Bulletin, vol. 23 No. 2, Jul. 1980, pp. 661-663.*
“Bit-by-Bit Erasable EEPROM with Single Transistor Per Bit”. Masuoka Conference: International Electron Devices Meeting, Washington D.C., Dec. 7-9, 1981, IEDM 81 pp. 20-23.*
“High Density Single-Poly Si Structure EEPROM with LB (Lowered Barrier Height) Oxide for VLSI's” Matsukawa et al., 1986.*
“Analysis and Modeling of Floating-Gate EEPROM Cells”, Kolodny et al., IEEE Transaction on Electron Devices, vol. Ed-33, No. 6, Jun. 1986.*
Modelling of Write/Erase and Charge Retention Characteristics of Floating Gate EEPROM Devices, A. Bhattacharyya, Solid-State Electronics, vol. 27, No. 10, pp. 899-906; 1986.*
“An EEPROM for Microprocessors and Custom Logic”, Cuppens et al., IEEE Journal of Solid-State Circuits, vol. SC-20, Apr. 1985.
Cappelletti Paolo G.
Corda Giuseppe
Riva Carlo
Galanthay Theodore E.
Jorgenson Lisa K.
Shingleton Michael B
STMicroelectronics S.r.l.
Venglarik Dan
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