EEPROM memory cell having improved breakdown characteristics and

Details EEPROM memory cell having improved breakdown characteristics and EEPROM memory cell having improved breakdown characteristics and

1985-09-27

1988-05-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365185, 3072385, G11C 1300

Patent

active

047424923

ABSTRACT:
Erasable programmable memory cell having a control gate, a row line and bit line is disclosed. Line driving circuitry coupled to the bit line and control gate applies a negative voltage to the bit line during the ERASE mode. The latter voltage is such that the voltage across the control gate, floating gate and drain of the floating gate transistor is sufficiently great to cause charging of the floating gate. The construction of the line driving circuit for applying the various voltages, including the negative erase voltage, to the control gate of the floating gate transistor is also disclosed. The line driving circuit is responsive to a control signal indicating the operating mode of the memory, and further includes blocking transistors so that the V.sub.pp voltage of the write operation is not coupled back to the circuit input which receives the control signal.

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IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, "High Voltage Regulation and Process Considerations for High-Density 5 V--Only E.sup.2 PROM's" by Oto et al., pp. 532-534.

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