EEPROM memory architecture

Details EEPROM memory architecture EEPROM memory architecture

2006-05-17

2008-08-19

Zarabian, A. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290

Reexamination Certificate

active

07414893

ABSTRACT:
An electrically erasable and programmable memory in which control gate transistors have been suppressed includes memory cells each with an access transistor and a floating gate transistor. A word line decoder is connected to word lines of the memory cells by a selection line connected to the gate terminals of the access transistors of the word line, and by a control gate line connected to the control gates of the floating gate transistors of the word line. Thus the voltage applicable to the gate terminals of the floating gate transistors is no longer limited by the voltage susceptible of being obtained on the source terminal of the control gate transistors.

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