Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-29
2002-04-09
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000
Reexamination Certificate
active
06369421
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an electrically erasable programmable read only memory (EEPROM) device and a method of manufacturing an EEPROM.
BACKGROUND ART
The escalating requirements for high density and performance associated with EEPROMs require increased transistor and circuit speeds, high reliability and increased manufacturing throughput. In a conventional EEPROM device formed from a single layer of polysilicon schematically illustrated in
FIG. 1
, write transistor
2
, read transistor
4
and sense transistor
6
form EEPROM memory cell
10
. Drain and source contacts are represented by D and S, respectively.
Adverting to
FIG. 1
, word line WL is connected to the control gates of write transistor
2
and read transistor
4
, respectively. Capacitor C
t
represents a tunnel oxide layer that capacitively couples the source region of write transistor
2
to floating gate electrode
8
of sense transistor
6
. Capacitor C
g
represents a gate oxide layer that separates the source region of sense transistor
6
from floating gate electrode
8
.
To write to EEPROM
10
, i.e., program the memory, a programming voltage is first applied to word line WL, which turns on write and read transistors
2
and
4
, respectively. By turning on transistor
2
, a write signal applied to the drain of write transistor
2
is coupled to the source of write transistor
2
. Similarly, when read transistor
4
is on, a read signal applied to the drain of read transistor
4
is coupled to the source of read transistor
4
.
Next, to program sense transistor
6
, a programming voltage is applied to the drain of write transistor
2
, with the source of sense transistor
6
grounded. The programming voltage capacitively couples floating gate electrode
8
of sense transistor
6
to write transistor
2
, due to the electric field created through C
t
and C
g
.
The programming voltage is set to a sufficient level to cause electron tunneling from floating gate electrode
8
to the source of write transistor
2
through C
t
, resulting in a net positive charge on floating gate electrode
8
. The positive net charge is sufficient to turn on sense transistor
6
and results in a logical “1” indication during subsequent read operations.
For example, during a subsequent read operation, a voltage is applied to word line WL and a read voltage applied to the drain of read transistor
4
, with both the drain of write transistor
2
and the source of sense transistor
6
grounded. A current then flows between the drain of read transistor
4
and the source of sense transistor
6
, when sense transistor
6
is on, thereby resulting in the indication of a logical “1”. When sense transistor
6
is not on, current does not flow and the read operation indicates a logical “0”.
As design features continually shrink in size, it becomes more difficult to reduce the size of EEPROMs due to conventional data retention requirements of the EEPROM, e.g., ten year data retention requirement. In conventional EEPROMs, the data retention requirement is met by employing a silicon dioxide (SiO
2
) tunnel oxide layer, represented by C
t
in
FIG. 1
, having a thickness of at least 90 Å.
The composition and thickness of the tunnel oxide layer directly affects the ability of electrons to tunnel from gate electrode
8
to the source of write transistor
2
. More particularly, the tunnel oxide layer directly affects programming speed and programming voltages required to program sense transistor
6
. One drawback attendant upon the data retention requirements of conventional EEPROMs is that the 90 Å SiO
2
tunnel oxide layer slows the programming speed of EEPROM
10
and raises the programming voltage required to program EEPROM
10
.
Accordingly, there exists a need for an EEPROM device and a method of manufacturing an EEPROM device having increased programming speed.
SUMMARY OF THE INVENTION
An advantage of the present invention is an EEPROM having increased programming speed.
Another advantage of the present invention is a method of manufacturing an EEPROM device with increased programming speed.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a an EEPROM comprising a semiconductor substrate, a first transistor and a tunnel oxide layer formed on the semiconductor substrate. The EEPROM also includes a second transistor coupled to the first transistor through the tunnel oxide layer with the tunnel oxide layer including a first region and a second region, the first region comprising a first dielectric material and the second region including the first dielectric material and a second dielectric material formed on the first dielectric material.
Another aspect of the invention is a method of manufacturing an EEPROM. The method includes forming a write transistor comprising a source region and a drain region in a semiconductor substrate. The method also includes forming a sense transistor comprising a source region, a drain region, a gate oxide layer formed on the semiconductor substrate and a floating gate electrode formed on the gate oxide layer. The method further includes forming a tunnel oxide layer on the semiconductor substrate between the first transistor and the floating gate electrode of the second transistor with the tunnel oxide layer including a first region and a second region, the first region comprising a first dielectric material and the second region including the first dielectric material and a second dielectric material formed on the first dielectric material.
Other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 5500816 (1996-03-01), Kobayashi
patent: 5917215 (1999-06-01), Chuang et al.
patent: 6087696 (2000-07-01), Li et al.
patent: 3220777 (1991-09-01), None
Japanese Kohai 3-220777 by Ishihara et al, 9/91, English translation.
Li Xiao-yu
Xiang Qi
Advanced Micro Devices , Inc.
Prenty Mark V.
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