Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-08-20
2004-02-03
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185130
Reexamination Certificate
active
06687167
ABSTRACT:
CROSS REFERENCE
This application claims foreign priority from Italian Patent Application No. RM2001A000525 filed on Aug. 30, 2001, the disclosure of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to non-volatile semiconductor memories and, more particularly, an EEPROM flash memory capable of being erased line by line.
2. Description of Related Art
A typical EEPROM flash memory comprises a multiplicity of memory cells formed on a substrate of semiconductor material and ordered in such a way as to form a matrix. Each cell has a body region of type p conductivity in which there are formed two regions (source and drain) of type n conductivity separated by a channel region. A floating gate electrode is arranged above the channel region and insulated from it by a thin layer of dielectric material. A control gate electrode extends above the floating gate electrode and is insulated from it by another layer of dielectric material.
The matrix cells have their source regions connected to a common terminal that, during the programming and reading phase, is generally connected to the negative (ground) pole of the supply source of the integrated circuit of which the memory forms part. The drain regions of the cells of each column of the matrix are connected to each other by means of common connection lines, generally referred to as bit or column lines. The control gate electrodes of the cells of each row are interconnected by means of common connection lines that are known as word lines or row lines.
Each matrix cell can be selected by means of a row decoder and a column decoder. A cell is selected by applying appropriate potentials to its terminals and its state can be ascertained by placing a sense amplifier in series with the bit line concerned.
When a memory cell is to be written or programmed, the bit line and the word line that identify it are brought to voltages higher than the common source voltage, for example, respectively 5V and 9V, thus causing “hot electrons” to pass from the body region to the floating gate electrode. The electrons that accumulate in the floating gate electrode bring about an increase of the cell's threshold voltage (by 2-4V).
When the cell has to be read, the common source terminal is connected to ground, a positive voltage is impressed on the bit line (drain), the word line (control gate) is brought to a higher voltage than the bit line, and the drain current is then measured by means of the sense amplifier. A non-programmed cell (which is conventionally assigned the logic level “1”) passes a relatively large current (for example 50 &mgr;A), while a programmed cell (logic level “0”) will pass a considerably smaller current.
When a cell is to be erased, a positive potential (5V for example) is applied to the common source terminal, a negative potential (−8V for example) is applied to the word line (control gate), and the bit line (drain) is allowed to float. In these conditions a strong electrical field is developed between the floating gate electrode and the channel region, so that the negative charge constituted by the accumulated electrons is extracted from the floating gate electrode due to the tunnel effect.
Erasure in an EEPROM flash memory of the conventional type is effected simultaneously either for all the matrix cells or for all the cells of a selected matrix sector. Thanks to this erasure method it is not necessary to have a selection transistor for each cell (as in the case of individually erasable EEPROM memories) and this makes it possible to fabricate small-size cells and therefore to obtain considerable advantages in terms of area and fabrication yield. However, this advantage has to be paid for in terms of reduced use flexibility of the memory.
With a view to extending the use of memories of this type to applications in which even a partial erasure of the memory is possible, it has been proposed to associate a buffer and appropriate transfer circuits with the memory in such a way as to temporarily save the contents of every sector in which a modification has to be effected. This solution requires supplementary integrated circuit area to be dedicated to the buffer and the transfer circuits, so that it is not always acceptable.
A method has also been proposed (see, U.S. Pat. No. 6,122,200) for erasing only one sector row at a time by applying a high negative voltage (−8V for example) to the row line to be erased, i.e. to the gate electrodes of all the cells of the row to be erased, and a high positive voltage (8V for example) to both the common node of all the source electrodes of the sector and the row lines of the cells that are not to be erased. When this is done, only the cells that are to be erased will effectively be in an erasure condition. But this solution is also associated with drawbacks. In particular, it creates two practical problems in the design of the row decoder circuits: the first is the realization of MOS transistors capable of withstanding the very high voltage drop caused by the simultaneous presence of both negative and positive voltages in the circuit (typically a high-voltage MOS transistor realized by present-day integrated circuit fabrication technologies cannot withstand more than 10V between two of its terminals); the second is the difficulty experienced in designing a decoder circuit capable of conciliating the functioning in the reading and programming phases, in which the selected row is at a high voltage and the non-selected rows are at ground potential (0V), with the functioning in the erasure phase, when the selected row (i.e. the one to be erased) is at a negative voltage and all the other rows are at a positive voltage.
One of the aims of the present invention is to propose an EEPROM flash memory that can be erased line by line and will permit this to be done without requiring decoder circuits with components capable of withstanding high voltages. Another aim of the invention is to propose a method of reading, programming and erasing a memory that will make it possible to optimize the functioning of the memory in the reading/programming phase and the erasing phase.
SUMMARY OF THE INVENTION
An EEPROM memory array includes a plurality of word lines. Each word line includes a first pull branch and second pull branch connected thereto. In operation of the memory array for reading/programming of memory cells associated with a certain word line, the first pull branch is activated for only that certain word line as a pull-up, with the second pull branches for the other word lines being activated as pull-downs. Conversely, in operation of the memory array for erasure of memory cells associates with a certain word line, the first pull branch is activated for only the certain word lines as a pull-down, with the second pull branches for the other word lines being activated as pull-ups.
REFERENCES:
patent: 6122200 (2000-09-01), Campardo et al.
patent: 6181606 (2001-01-01), Choi et al.
patent: 6587375 (2003-07-01), Chung et al.
Jenkens & Gilchrist P.C.
Phung Anh
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