EEPROM device with plurality of memory strings made of floating

Details EEPROM device with plurality of memory strings made of floating EEPROM device with plurality of memory strings made of floating

1988-12-30

1990-10-09

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365184, 365218, 357 235, G11C 1140

Patent

active

049624814

ABSTRACT:
An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the floating gate transistors in the lower memory strings being respectively connected to first and second select lines, each other upper word lines, third and fourth select lines and each other lower word lines. The drains of the first and second transistors are connected to the column line through a single contact hole; the other ends of the serial connections in the upper memory strings are connected to the reference line adjacent thereto; and means for connecting the other ends of the serial connections in the lower memory strings to the reference line adjacent thereto.

REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4233526 (1980-11-01), Kurogi et al.
patent: 4467453 (1984-08-01), Chiu et al.
patent: 4500975 (1985-02-01), Shirato
patent: 4580247 (1986-04-01), Adam
patent: 4648074 (1987-03-01), Pollachek
Symoposium on VLSI Technology, May 1986, pp.-89 -90, "A High Density EPROM Cell and Array" by Stewart et al., Digest of Tech. Papers.
IBM Technical Disclosure Bulletin, vol. 24, No. 7B, Dec. 81, pp. 3811-3812 "Electrically Alterable Non-Volatile Logic Circuits" by Kotecha.
Symposium on VLSI Circuit, Digest of Technical Papers, 1988 VLSI Research Center, Toshiba Corp., pp. 33-34, "A New Cell for Ultra High Density 5V-only EEPROMs" by Shirota et al.

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