EEPROM device having selecting transistors and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S257000

Reexamination Certificate

active

11336751

ABSTRACT:
An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

REFERENCES:
patent: 4780431 (1988-10-01), Maggioni et al.
patent: 6103573 (2000-08-01), Harari et al.
patent: 6221717 (2001-04-01), Cremonesi et al.
patent: 6420754 (2002-07-01), Takahashi et al.

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