EEPROM device and method of fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S295000, C257S298000, C257S314000, C257S315000, C257S318000

Reexamination Certificate

active

10872858

ABSTRACT:
A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent to the memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent to the select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.

REFERENCES:
patent: 6555869 (2003-04-01), Park
patent: 11-111936 (1999-04-01), None
patent: 2001-210730 (2001-08-01), None
Japan Patent Abstracts of Publication No. 2001-210730.
Japan Patent Abstracts for Publication No. 11-111936.

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