Static information storage and retrieval – Read/write circuit – Erase
Patent
1992-02-10
1992-11-24
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Erase
365149, 365185, 257317, G11C 1300, G11C 1142
Patent
active
051669048
ABSTRACT:
An electrically readable and writable memory cell structure and array architecture formed on a semiconductor substrate to achieve very high speed programming with low power. The cell includes a superior storage capacitor structure including a textured surface of at least one of the plates and a dielectric sandwich between the plates that prevents charge loss in all modes of the electrical operation of the memory cell while increasing the capacitance of the capacitor which also reduces the programming (writing a first logical state) voltage of the memory cell. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.
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