EEPROM cell array structure with specific floating gate shape

Details EEPROM cell array structure with specific floating gate shape EEPROM cell array structure with specific floating gate shape

2002-09-05

2003-12-16

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000

Reexamination Certificate

active

06664587

ABSTRACT:

TECHNICAL FIELD
This invention pertains to semiconductor memory cells and arrays, more particularly to electrically erasable programmable read only memories.
BACKGROUND
Erasable programmable read only memories (EPROMS) and electrically erasable programmable read only (EEPROMs) are well known in the art. These devices have the ability to store data in non-volatile fashion, while also being capable of being erased and rewritten as desired. EPROM devices are typically erased by exposing the integrated circuit device to ultraviolet radiation, while EEPROMs allow erasure to be performed electrically.
One form of EEPROM device includes a so-called “split-gate” electrode, in which the control gate includes a first portion overlaying a floating gate and a second portion directly overlaying the channel. Such a split gate structure is described in a 5-Volt-Only Fast-Programmable Flash EEPROM Cell with a Double Polysilicon Split-Gate Structure by J. Van Houdt et al, Eleventh IEEE Non-Volatile Semiconductor Workshop, February 1991, in which charge is injected into the floating gate from the source side of the cell. U.S. Pat. No. 4,652,897 describes an EEPROM device which does not utilize a split-gate, but which also provides injection to the floating gate from the source side of the device.
As described in the above referenced U.S. Pat. No. 4,652,897, memory cells are typically arranged in an array, as is well known in the art. One form of such an array utilizes buried diffusions, in which source and array regions are covered with a fairly thick layer of insulating material. This is shown for example, in U.S. Pat. Nos. 4,151,020; 4,151,021; 4,184,207; and 4,271,421. Such buried diffusion devices often utilize a virtual ground approach, in which columns connecting the sources of a first column of memory cells also serves to connect drains of an adjacent column of memory cells.
While many EEPROM devices utilize two layers of polycrystalline silicon, one for the formation of the floating gate, and the other for the formation of the control gate and possibly electrical interconnects, other EEPROM devices utilize three layers of polycrystalline silicon. For example, U.S. Pat. No. 4,302,766 provides a first polycrystalline silicon layer for the floating gate, a second polycrystalline silicon layer for the control gate, and a third polycrystalline silicon layer coupled through an erase window to a portion of the first polycrystalline silicon layer for use during erasure of the cell. U.S. Pat. No. 4,331,968 also uses a third layer of polycrystalline silicon to form an erase gate, while U.S. Pat. No. 4,462,090 forms an addressing gate electrode utilizing a third layer of polycrystalline silicon. U.S. Pat. Nos. 4,561,004 and 4,803,529 also use three layers of polycrystalline silicon in their own specific configurations.
Japanese Patent Publication 61-181168 appears to utilize three layers of polycrystalline silicon to provide additional capacitive coupling to the floating gate. Japanese Patent Publication 63-265391 appears to pertain to a buried diffusion array, possibly utilizing virtual grounds.
European Patent Application 0373830 describes an EEPROM in which two polycrystalline silicon layers are used, with the second layer of polycrystalline silicon having two pieces, one of which provides the erase function, and one of which provides the steering function. “A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate on its Source Side” by K. Naruke et al. IEDM-89-603 and U.S. Pat. No. 4,794,565 describe an EEPROM utilizing a side wall select gate located on the source side of the field effect transistor.
“EPROM Cell With High Gate Injection Efficiency” by M. Kamiya et al. IEDM 82-741, and U.S. Pat. No. 4,622,656 describe an EEPROM device in which a reduced programming voltage is provided by having a highly doped channel region under the select gate, and the channel region under the floating gate being either lightly doped or doped to the opposite conductivity type, thereby providing a significant surface potential gap at the transition location of the channel.
In recent years there has been significant interest in producing high capacity FLASH memory devices which use split-gate, source-side hot electron programming, is place of the more conventional drain-side channel hot electron (CHE) mechanism.
The reasons for this include its inherently lower write power requirement ({fraction (1/10)}th that of CHE or less), facilitating low voltage operation and higher write speeds via increased parallelism. In addition, the split gate structure is not susceptible to “overerase” related problems (a problem for single gate FLASH memories such as ETOX), and does not experience programming difficulty due to strong overerase, which can hinder programming after an erasure operation in split-gate CHE programming devices.
In view of these benefits, SunDisk Corporation has patente FLASH memory cell and array variants which use source side injection integrated with SunDisk's proprietary thick oxide, poly-to-poly erase tunneling technology, to make a highly scalable, reliable, low power programming cell (D. C. Guterman, G. Samachiasa, Y. Fong and E. Harari, U.S. Pat. No. 5,313,421).
The concept of a multi-bit storage non-volatile cell using a split gate structure was described by G. S. Alberts and H. N. Kotecha (Multi-bit storage FET EAROM cell, IBM Technical Disclosure Bulletin, Vol. 24 No. 7A, p. 3311, Dec. 1981). They describe a two-poly, three transistor element-in-series cell, in which the center transistor's channel is controlled directly by the poly 2 control gate (which also serves as the cell select gate), and each of the two end transistor channels are controlled by corresponding poly 1 floating gates, which in turn are capacitively coupled to the control gate, thereby realizing a plurality of bits in the one physical cell structure.
Recently, at the 1994 IEDM, Bright Microelectronics along with Hyundai presented a similar dual-bit split-gate cell, integrated into a contactless, virtual ground array, and using source side injection programming (Y. Y. Ma and K. Chang, U.S. Pat. No. 5,278,439—referred to henceforth as the Ma approach). One structural difference here from the IBM approach is their separation of the capacitively coupling control gates, which are formed in poly 2, and the select gate, which is formed in poly 3.
In the Ma approach, they use “conventional” negative control gate driven tunneling through an ultra-thin poly 1 gate oxide (about 100 Å or less). This erase approach poses some serious limitations. Erase of one of the two storage transistors uses floating gate to drain tunneling through the ultra-thin oxide, accomplished by biasing the drain to 7 v and corresponding control gate to −10 v. Because both of these lines run perpendicular to the select gate, this forces a block of cells which are to be simultaneously erased (e.g. a sector) to be bit line oriented, as opposed to the more conventional word line (select gate) oriented block; i.e. its sector must be column organized and thus it cannot be row organized. (For example, a sector could be two columns of floating gates straddling a bit line/diffusion, including the right hand floating gates of the left side cells' floating gate pair plus the left hand floating gates of the right side cells.) This leads to the following disadvantages in the Ma implementation: (1) Limited to column sector architecture; i.e. cannot readily support the higher read performance row oriented sector architecture. (Since here, within a sector, both erase anode and corresponding control gates run perpendicular to row line direction, this precludes the massively parallel “chunk” implementation of the row oriented sector, which can simultaneously access large numbers of cells within that sector).
(2) Requires ultra-thin, approximately 100 Å, tunneling oxide, imposing following limitations:
Scaling limitation associated with pushing the limits of usable oxide thicknesses, plus the additional area needs associated with maintaining a

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