EEPROM array using 2-bit non-volatile memory cells and...

Details EEPROM array using 2-bit non-volatile memory cells and... EEPROM array using 2-bit non-volatile memory cells and...

1999-02-04

2001-07-03

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S063000, C365S185050, C365S218000

Reexamination Certificate

active

06256231

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to non-volatile memory cells. More specifically, the present invention relates to a method and structure of using a 2-bit flash memory cell to form an electrically erasable programmable read only memory (EEPROM) array.
RELATED ART
FIG. 1
is a cross sectional view of a conventional 1-bit non-volatile semiconductor memory cell
10
that utilizes asymmetrical charge trapping. 1-bit memory cell
10
, which is fabricated in p-type substrate
12
, includes n+ source region
14
, n+ drain region
16
, channel region
17
, silicon oxide layer
18
, silicon nitride layer
20
, silicon oxide layer
22
, and control gate
24
. Oxide layer
18
, nitride layer
20
and oxide layer
22
are collectively referred to as ONO layer
21
. Memory cell
10
operates as follows. A programming operation is performed by connecting source region
14
to ground, connecting drain region
16
to a programming voltage of about 9 Volts, and connecting control gate
24
to a voltage of about 10 Volts. As a result, electrons are accelerated from source region
14
to drain region
16
. Near drain region
16
, some electrons gain sufficient energy to pass through oxide layer
18
and be trapped in nitride layer
20
in accordance with a phenomenon known as hot electron injection. Because nitride layer
20
is non-conductive, the injected charge remains localized within charge trapping region
26
in nitride layer
20
.
Memory cell
10
is read by applying 0 Volts to the drain region
16
, 2 Volts to the source region
14
, and 3 volts to the gate electrode. If charge is stored in charge trapping region
26
(i.e., memory cell
10
is programmed), then memory cell does not conduct current under these conditions. If there is no charge stored in charge trapping region
26
(i.e., memory cell
10
is erased), then memory cell
10
conducts current under these conditions. The current, or lack of current, is sensed by a sense amplifier to determine the state of memory cell
10
.
Note that the polarity of the voltage applied across source region
14
and drain region
16
is reversed during the program and read operations. That is, memory cell
10
is programmed in one direction (with source region
14
grounded), and read the opposite direction (with drain region
16
grounded). As a result, the read operation is referred to as a reverse read operation. Memory cell
10
is described in more detail in U.S. Pat. No. 5,768,192.
Memory cell
10
can also be controlled to operate as a 2-bit non-volatile semiconductor memory cell. To accomplish this, memory cell
10
is controlled to use a second charge trapping region in nitride layer
20
, which is located adjacent to source region
14
.
FIG. 2
illustrates both the first charge trapping region
26
(described above in connection with FIG.
1
), and the second charge trapping region
28
in dashed lines. The second charge trapping region
28
is used to store a charge representative of a second bit. The second charge trapping region
28
is programmed and read in a manner similar to the first charge trapping region
26
. More specifically, the second charge trapping region
28
is programmed and read by exchanging the source and drain voltages described above for programming and reading the first charge trapping region
26
. Thus, the second charge trapping region
28
is programmed by applying 0 Volts to drain region
16
, applying 9 Volts to source region
14
and applying 10 Volts to control gate
24
. Similarly, the second charge trapping region
28
is read by applying 0 Volts to source region
14
, 2 Volts to drain region
16
, and 3 Volts to control gate
24
.
Note that because nitride layer
20
is non-conductive, the charges stored in the first and second charge trapping regions
26
and
28
remain localized within nitride layer
20
. Also note that the state of the first charge trapping region
26
does not interfere with the reading of the charge stored in the second charge trapping region
28
(and vice versa). Thus, if the first charge trapping region
26
is programmed (i.e., stores charge) and the second charge trapping region
28
is not programmed (i.e., does not store charge), then a reverse read of the first charge trapping region will not result in significant current flow. However, a reverse read of the second bit will result in significant current flow because the high voltage applied to drain region
16
will result in unperturbed electronic transfer in the pinch off region adjacent to first charge trapping region
26
. Thus, the information stored in the first and second charge trapping regions
26
and
28
is read properly.
Similarly, if both the first and second charge trapping regions are programmed, a read operation in either direction will result in no significant current flow. Finally, if neither the first charge trapping region
26
nor the second charge trapping region
28
is programmed, then read operations in both directions will result in significant current flow.
Because the 1-bit and 2-bit implementations of memory cell
10
are relatively new, the manner of using this memory cell
10
in a memory cell array has not yet been fully developed. It would therefore be desirable to have a memory array structure that allows memory cell
10
to be implemented as an electrically erasable programmable read only memory (EEPROM). For purposes of this disclosure, an EEPROM array is defined as a non-volatile memory array that can be erased on a word-by-word basis. This is in contrast to a flash memory array, which is defined as a non-volatile memory array that cannot be erased on a word-by-word basis, but which must be erased in blocks. It would further be desirable if the EEPROM array architectures could be fabricated using a standard flash process.
SUMMARY
Accordingly, the present invention provides structures and methods for implementing an EEPROM array using 2-bit non-volatile memory cells. As described above, each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit.
In one embodiment, the EEPROM array includes an array of 2-bit memory cells arranged in a plurality of rows and columns. Each row of memory cells shares a word line, which provides a common connection to the control gates of the memory cells in the row. Also within each row, the first charge trapping region of each memory cell is coupled to the second charge trapping region of an adjacent memory cell by a diffusion bit line. Note that for purposes of the present disclosure, a charge trapping region is defined as being “coupled” to its nearest diffusion bit line, even though there is no physical connection between the diffusion bit line and the charge trapping region. In this embodiment, each diffusion bit line provides connections to memory cells in a plurality of rows.
In one embodiment, an erase operation is performed by applying a voltage of about 0 Volts to the word line of the selected memory cell, and a voltage of about 8 Volts to the diffusion bit line of the selected memory cell. Other voltages can be used in other embodiments. Because adjacent memory cells share the same word line and the same diffusion bit line, erasing the first charge trapping region of a memory cell will incidentally erase the second charge trapping region of the adjacent memory cell. Moreover, memory cells in other rows that are coupled to the same diffusion bit line will also receive the erase voltage of 8 Volts, potentially subjecting these memory cells to erase conditions.
The present invention compensates for the above-described erase conditions as follows. A storage device is coupled to the diffusion bit lines of the array. A memory control circuit is coupled to control the EEPROM array and the storage device. Prior to erasing the first charge trapping region of a first memory cell, the memory control circuit reads a plurality of bits from the array, and causes these bits to be written to the storage device. The bits read from the array are selecte

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