EEPROM and EEPROM manufacturing method

Details EEPROM and EEPROM manufacturing method EEPROM and EEPROM manufacturing method

2005-07-05

2005-07-05

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C438S257000

Reexamination Certificate

active

06914288

ABSTRACT:
A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

REFERENCES:
patent: 4377857 (1983-03-01), Tickle
patent: 4477825 (1984-10-01), Yaron et al.
patent: 4794562 (1988-12-01), Kato et al.
patent: 6157058 (2000-12-01), Ogura
patent: 6291851 (2001-09-01), Matsumoto et al.
patent: 6323517 (2001-11-01), Park et al.
patent: A-59-205763 (1984-11-01), None
patent: A-61-181168 (1986-08-01), None
Lucero, et al., “A 16 kbit Smart 5 V-Only EEPROM with Redundancy,”IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 539-544.

Affiliated with

Also associated with

Rating

EEPROM and EEPROM manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with EEPROM and EEPROM manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EEPROM and EEPROM manufacturing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3415848