Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-09
2003-09-23
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000
Reexamination Certificate
active
06624467
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to electrically erasable/programmable read only memory (EEPROM) cells. More particularly, the invention relates to modifications to active area masks to avoid tunnel dielectric window size variations and reduce cell area.
Conventional nonvolatile memory cells include EPROM, Flash and EEPROM cells. EPROM cells are electrically programmed by moving electrons onto the cell's floating gate via hot electron injection, and optically erased (removing electrons from the floating gate) by exposure of the cell to UV radiation. EEPROM cells are both electrically programmed and electrically erased by moving electrons on and off the cell's floating gate via Fowler-Nordheim tunneling. Flash cells have elements of both EPROMs and EEPROMs: they, are electrically programmed by hot electron injection and electrically erased by Fowler-Nordheim tunneling. Each of these memory cells have particular applications for which they are best suited.
EEPROM cells have the advantages that they need not be exposed to UV radiation for erasure, and they do not require the cell circuitry necessary for generating fields sufficient for hot electron injection. Therefore, EEPROMs are preferred in applications where these requirements would make it impractical or impossible to use an EPROM or FLASH cell.
FIG. 1
shows a perspective view of a typical EEPROM cell. The cell
30
is a single polysilicon EEPROM cell. As such, it does not have a polysilicon control gate, but instead has a heavily doped diffusion region in the cell's substrate which is capacitively coupled to its floating gate. The cell
30
includes a single polysilicon floating gate structure
32
which performs three functions. At a first end, a tunnel extension
34
of floating gate
32
acts as an electrode in the two terminal device used for tunneling electrons from a heavily doped N
+
implant
35
(also referred to as a programming Memory Diffusion or MD) through a tunnel oxide
36
(often about 80 Å thick) onto floating gate structure
32
. At the other end of this floating gate, a wide area plate
38
is employed as one electrode of a capacitor enabling the floating gate
32
to be raised to a high voltage (e.g., about 6 to 11 volts) by capacitively coupling a programming voltage (e.g., about 9 to 13 volts) from a second electrode
40
(heavily doped N+silicon, referred to herein as a control gate memory diffusion) through an oxide
42
(often about 180 Å thick). Between these two ends is a section of polysilicon that forms the gate
44
of a read transistor (N
2
).
The read transistor (N
2
) is connected in series with a word line transistor. (N
1
) having a gate
46
forming part of a word line (also referred to as a row line)
31
. The read and word line transistors separate a sense amp negative (−) input
48
(a source line) from a sense amp positive (+) input
50
(a drain line). Charging the floating gate
32
by tunneling electrons onto it (through tunnel oxide
36
) raises the threshold voltage of the read transistor (EEPROM cell
30
is programmed). This shuts off the channel between the sense amp inputs, even when the adjacent word line transistor is turned on. Tunneling electrons off the floating gate
32
reduces the read transistor threshold voltage to negative values, effectively turning this device on (EEPROM cell
30
is erased). The word line transistor in series then controls the signal path between the two sense amp inputs
48
and
50
.
The EEPROM cell is programmed or erased by charging or discharging, respectively, the floating gate
32
. In order to tunnel electrons onto floating gate
32
, a high voltage must be applied to the control gate memory diffusion
40
. At the same time, the write column
56
is grounded and the write column transistor (N
3
) is turned on by, for example, selecting the row line
31
with, for example, 5 volts. The sense amp (−) input
48
can be biased from about 5 volts to a high voltage to assist tunneling electrons onto the floating gate
32
. The voltage on the control gate memory diffusion
40
is capacitively coupled to the floating gate
32
as is the sense amp (−) input 48 voltage. The resulting positive voltage on floating gate
32
is sufficient to cause tunneling onto floating gate
32
through the tunnel oxide
36
where it intersects the floating gate (the tunnel oxide window
36
a
(shaded)), thereby programming the EEPROM cell
30
.
In order to tunnel electrons off floating gate
32
, a high voltage must be applied to memory diffusion
35
while ground is applied to the second heavily doped N+ implant (control gate memory diffusion)
40
which underlies and is capacitively coupled to the wide area plate
38
. During this process, ground is also applied to sense amp (−) input
48
. The application of high voltage to memory diffusion
35
is accomplished through a write column
56
and a write column select transistor (N
3
) including (i) a diffusion region
54
conductively connected to write column
56
for data input, (ii) a source/drain diffusion
58
electrically connected to memory diffusion
35
, and (iii) a gate electrode
60
, which is part of row line
31
. When a sufficient potential is applied to the gate
60
of the write column select transistor through row line
31
while a write signal is applied through write column
56
, electrons can tunnel off of the floating gate
32
to erase the EEPROM cell.
A further description of a typical EEPROM cell and its functional elements is available the publication “EPM7032 Process, Assembly, and Reliability Information Package” available from Altera Corporation of San Jose, Calif. That document is incorporated herein by reference for all purposes.
In EEPROM cells, it is very important to have a tunnel dielectric (TD) window (defined here as the cross-section of the overlapping TD and active layers) that is free of any undue window size variations that effect the cell performance. It is thus important to minimize variations in size of the TD window that may occur naturally due to processing variations.
FIG. 2
shows conventional masks for the active area and tunnel dielectric which intersect to form the tunnel windows
202
and
212
for two adjacent EEPROM cells
200
and
210
, respectively, of an EEPROM array on a semiconductor die
220
. Referring to EEPROM cell
200
as an example, the active area mask
204
is narrowed in the region of the tunnel dielectric mask
206
in order to provide the smallest tunnel window area possible, and allow for the smallest possible control gate area (not shown), thereby reducing the EEPROM cell's overall size.
In this figure, dimension “A” is the cell height which needs to be minimized in order to achieve the smallest possible die area. Dimension “B” is the inter-cell distance which typically must be greater than some minimum value to avoid active-to-active area current leakage between adjacent cells. The extent to which the active area mask extends beyond its overlap with the TD layer mask is labeled as dimension “C”. The width of the tunnel dielectric is labeled as dimension “W” of the tunnel dielectric mask
206
. The width of the active area mask
204
is labeled as dimension “D.” The tunnel window
202
,
212
area, therefore, is defined by W×D. These labels are used to assist is describing active area masks throughout the present application.
Two separate effects may be responsible for TD window size variations during wafer processing. First of all, there is typically a loss of resolution in the transfer of the image of the desired feature from a mask to a photoresist, particularly in corners and tight spaces of an image. This results in a rounding of corners which generally decreases the size of the feature produced by the mask. In EEPROM processing, this phenomenon may reduce the size of the active area in the final product resulting from the active area mask. The active area is typically further reduced in size by a physical process, n
Liang Minchang
Madurawe Raminda U.
McElheny Peter J.
Smolen Richard G.
Beyer Weaver & Thomas LLP
Pham Long
Weiss Howard
LandOfFree
EEPROM active area castling does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with EEPROM active area castling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EEPROM active area castling will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3108438