eDRAM hierarchical differential sense AMP

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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Details

C365S191000, C365S196000, C365S202000, C365S205000

Reexamination Certificate

active

07821858

ABSTRACT:
In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.

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