Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-24
2003-09-09
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S368000
Reexamination Certificate
active
06617656
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an EDMOS (extended drain MOS) having a lattice type drift region and a method of manufacturing the same. More particularly, the invention relates to an EDMOS having a lattice type drift region and a method of manufacturing the same in which a lattice of an n type impurity (hereinafter, called ‘n lattice’) having a high concentration and a lattice of a p type impurity (hereinafter, called ‘p lattice’) having a low concentration form a drift region and a pn junction to have a high breakdown voltage and a low on resistance.
2. Description of the Prior Art
FIG. 1
is a perspective view of a conventional nEDMOS device.
Referring now to
FIG. 1
, a p well region
104
is formed in a given region of a p type silicon substrate
101
. An n-drift region
107
as an extended drain region is then formed in a given region of the p well region
104
. Field oxide films
109
and
109
a
are formed on a given region of the p type silicon substrate
101
. An n+ source region
112
and a p+ source contact region
114
are adjacently formed on another given regions of the p well region
104
. Thereafter, an n+ drain region
113
is formed in a given region of the n− drift region
107
. A polysilicon gate electrode
111
in which the gate oxide film
110
is intervened is formed on a given region of the p type silicon substrate
101
. At this time, the n− drift region
107
is extended from an edge of the polysilicon gate electrode
111
to the bottom of n+ drain region
113
. Further, a source electrode
116
connected to the n+ source region
112
and the p+source contact region
114
, and a drain electrode
117
connected to the n+ drain region
113
are formed on an insulating layer
115
.
In the conventional nEDMOS constructed above, the n− drift region
107
is composed of a single layer doped an n type impurity. The breakdown voltage and the on resistance of the device are determined by the concentration of an n type impurity, the depth and length of the drift region, and the like. In other words, if the concentration of an n type impurity in the n− drift region
107
is increased, the on resistance is lowered but the breakdown voltage of the device is lowered. On the contrary, if the concentration of an n type impurity in the n− drift region
107
is reduced, the breakdown voltage of the device is increased and the on resistance is also increased.
As such, in order to increase the concentration of an impurity in the n drift region
107
of the conventional nEDMOS device, there are many limits in the structure and manufacturing process of the device. Therefore, it is difficult to realize a device simultaneously having a high breakdown voltage and a low on resistance.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide an EDMOS device and a method of manufacturing the same capable of simultaneously obtaining a high breakdown voltage and a low on resistance.
Another object of the present invention is to provide an EDMOS device having a lattice type drift region and a method of manufacturing the same capable of simultaneously obtaining a high breakdown voltage and a low on resistance, in such a way that an n lattice having a high concentration and a p lattice having a low concentration form a pn junction.
The present invention can improve the breakdown voltage and the on resistance characteristics of the nEDMOS device by forming a drift region composed of an n lattice and p lattice. In the nEDMOS device proposed by the present invention, an impurity concentration of the n lattice is much higher than that of an n− drift region of the conventional device, and an impurity concentration of the p lattice is similar to that of the p well. Therefore, as the n lattice having a high concentration and the p lattice having a low concentration are adjacently and alternately formed to a pn junction, the depletion layer is rapidly extended by applying a drain voltage. Therefore, according to the present invention, the breakdown voltage of the nEDMOS device become higher and the on resistance of the nEDMOS device become lower than those of the conventional nEDMOS device due to a high impurity concentration of the n lattice.
Further, the nEDMOS device having the drift region of a lattice structure according to the present invention has an advantage that it can be manufactured together with a conventional CMOS device. Therefore, an optimum of the process and device structure is necessary to easily form a depletion layer between a pn junction while increasing the concentration of the n lattice. The optimum is accomplished by controlling the impurity concentration, size and depth of the n lattice and the p lattice, and the distance between the n lattice and the p lattice.
In order to accomplish the above object, an EDMOS device having a lattice type drift region according to the present invention, is characterized in that it comprises a well region formed in a given region of a silicon substrate; a lattice type drift region formed in a given region of the well region and composed of a first lattice and a second lattice alternately arranged; a field oxide film formed on the silicon substrate and overlapped with a portion of the well region or a portion of the well region and the drift region; a drain region formed in a given region of the drift region; a diffusion region formed below the drain region; a source region and a source contact region formed in the well region; a gate electrode formed on the silicon substrate of the well region, wherein a gate insulating film is intervened between the gate electrode and the silicon substrate; a source electrode connected to the source region and the source contact region via a contact hole formed in an insulating film; and a drain electrode connected to the drain region via a contact hole formed in the insulating film.
Further, a method of manufacturing an EDMOS device having a lattice type drift region is characterized in that it comprises the steps of forming a well region in a given region of a silicon substrate; alternately implanting first impurity ions in a given region of the well region to form a lattice type drift region having a first lattice and a second lattice which are alternately arranged, wherein the first lattice is implanted by the first impurity ions; forming a field oxide film on a given region of the silicon substrate; implanting second impurity ions in the well region to control a threshold voltage; forming a gate insulating film and a polysilicon film on the silicon substrate of the well region, and then patterning the polysilicon film to form a gate electrode; implanting third impurity ions in the well region and the drift region to form a source region and a drain region, respectively; implanting fourth impurity ions in the well region to form a source contact region connected to the source region; forming an insulating film on an entire structure, and then forming contact holes in the insulating film to expose the source region, the drain region and the gate electrode; and forming metal wires connected to the source region, the drain region and the gate electrode via the contact holes, respectively.
REFERENCES:
patent: 6198141 (2001-03-01), Yamazaki et al.
patent: 6207994 (2001-03-01), Rumennik et al.
patent: 6512268 (2003-01-01), Ueno
patent: 2001/0052601 (2001-12-01), Onishi et al.
patent: 2000252297 (2000-09-01), None
High Performance Stacked LDD RF LDMOSFET by Jun Cai et al. Proceedings of 2001 International Sym. on Power Semi. Devices & ICs, Osaka.
120 V Interdigitated-Drain LDMOS (IDLDMOS) on SOI Substrate Breaking Power LDMOS Limit by Shuming Xu et al. IEEE Transactions on Electron Devices, vol. 47, No. 10, Oct. 2000.
Kim Jong Dae
Lee Dae Woo
Park Il Yong
Roh Tae Moon
Yang Yil Suk
Blakely & Sokoloff, Taylor & Zafman
Electronics and Telecommunications Research Institute
Wilson Allan R.
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