Edge triggered latch with symmetrical paths from clock to...

Details Edge triggered latch with symmetrical paths from clock to... Edge triggered latch with symmetrical paths from clock to...

2002-05-14

2002-12-10

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S219000

Reexamination Certificate

active

06492856

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to logic circuits and in particular to D-type latches which have equal time delays from a clock to either an inverting output or a non-inverting output.
BACKGROUND INFORMATION
Latches or flip flops are key elements for many very large scale integrated (VLSI) circuit applications. The data or D-type latch is a particular latch type that is used for sampling data with a clock and holding a sampled value. The D-type latch may be designed to be either transparent or edge triggered. A transparent D-type latch is designed so that the output tracks the input when the clock is in one logic state and a latching function holds the output when the clock is in the other logic state. An edge triggered D-type latch allows the output to track the input only for a time window after the clock changes states. Edge triggered D-type latches may be either positive or negative edge triggered.
VLSI chips typically employ many latches and latch performance and power consumption is a continual concern. One latch parameter that is of particular interest is the time, from a clock edge, required to generate latched differential outputs and how well this time is balanced for each output. A perfectly balanced differential output latch would have the same time delay from a sampling clock edge to the generation of the inverting and non-inverting outputs. Well balanced differential output latches, and in particular D-type latches, are a critical component in many high performance logic systems. In digital communications systems where differential signaling is a common practice, the balance of latch differential outputs directly contributes to timing jitter and skew. Timing jitter and skew result in performance degradation and may be a limit to the total distance of digital data transmission. In order to minimize this problem, latches with well-balanced differential outputs are essential. There are various circuit configurations for latches in the art which are used for various logic applications. A D-type latch that gives one of the best characteristics in terms of power consumption and performance, and thus is widely used in high performance systems, is the so called hybrid-latch flip flop (HLFF) shown in FIG.
1
. Despite its fast performance and relatively low power consumption, the HLFF latch
100
produces a delay difference from the clock
119
to differential outputs Q
122
and Q
N
121
. In order to obtain balanced differential outputs, two copies of this latch are used by some designers, a method which causes a near doubling of power consumption per latch.
Therefore, there is a need for a D-type latch with balanced differential outputs and a reduced power consumption over the prior art.
SUMMARY OF THE INVENTION
A D-type latch uses a clock and an inverted clock, delayed a predetermined time from the clock, to generate a clock window time (pulse). Two input logic circuits sample a data input and an inverted data input. In one embodiment the two input logic circuits share a common pull-down transistor which is turned ON by one of the clock signals. Two output logic circuits receive the sampled data outputs, the clock, and the inverted clock and generate a latch output and an inverted latch output. The first output logic circuit generates the latch output while receiving the sampled data output and the second output logic circuit generates the inverted latch output while receiving the inverted sampled data output. The latch output from the first output logic circuit is cross coupled as a feedback signal to pull-up and pull down circuits in the second output logic circuit. Likewise the inverted latch output from the second output logic circuit is cross coupled as a feedback signal to pull-up and pull-down circuits in the first output logic. The clock window time is generated in both the input logic circuits and the output logic circuits to assert latch output states determined by states on the data inputs. The cross coupled feedback of the latch outputs serves to both enforce the asserted states as well as hold the latch outputs after the clock window time. In another embodiment, the pull-down circuits in the input logic circuits do not share a common pull-down device. The D-type latch has equal circuit paths from the clock inputs to the latch outputs as well as low power, and minimum delay. The cross-coupled feedback of latch outputs improves delay, generates precise differential output transitions and lowers power consumption.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 4873456 (1989-10-01), Olisar et al.
patent: 5936449 (1999-08-01), Huang
patent: 6163189 (2000-12-01), Ogawa
patent: 6222404 (2001-04-01), Mehta et al.
patent: 6239640 (2001-05-01), Liao et al.

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