Edge-triggered latch with balanced pass-transistor logic...

Details Edge-triggered latch with balanced pass-transistor logic... Edge-triggered latch with balanced pass-transistor logic...

2001-03-15

2002-09-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S051000, C327S052000

Reexamination Certificate

active

06445217

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to storage devices within digital systems, and in particular to an improved edge-triggered latch that combines the data and clock generation path utilizing pass-transistor logic.
2. Description of the Related Art
Digital circuits, such as microprocessors and memory devices, typically use flip-flops as temporary storage devices. The most basic type of flip-flops operate with signal levels and are often referred to as latches. A latch with clock pulses as its control input is essentially a flip-flop that is triggered every time the clock pulse goes to a one or zero logic level. For ease of reference, it will be assumed that, as utilized herein, “latch” incorporates flip-devices and all clock-controlled latches.
Several categories of latches are known in the art including level-sensitive, master-slave, and edge-triggered. The present invention is directed to edge-triggered latch design. With reference to
FIG. 1
, there is depicted a conventional D-latch
100
. In accordance with well-known D-latch design standards, D-latch
100
has two inputs, D (data) at a data input node
106
, and C (control) at a clock input node
108
. D-latch
100
generates a differential output at an output node
114
and a complementary output node
112
. The outputs at nodes
112
and
114
cannot change state while the clock input at node
108
is at a logic
0
regardless of the value of D at data input node
106
. A graphical representation of the input and output signals to and from D-latch
100
is provided in FIG.
2
.
D-latch
100
is a positive edge-triggered latch, meaning that it triggers a data input at input node
106
only during a positive transition of a clock signal C. Two such positive clock signal transitions,
212
and
214
, are depicted in FIG.
2
. Pulse generating circuitry including Complementary Metal Oxide Semiconductor (CMOS) P-type Field Effect Transistors (PFETs) P
2
and P
3
, and N-type Field Effect Transistors (NFETs) N
3
, N
5
, N
4
, and N
6
, is utilized to enable edge-triggered data propagation within D-latch
100
as follows.
Three CMOS inverters, I
1
, I
2
, and I
3
produce a delayed complementary version of control signal C, illustrated in
FIG. 2
as {overscore (C)}
dd
. Control signal C is logically ANDed with its delayed complementary counterpart {overscore (C)}
dd
by series NFET pairs N
3
and N
5
, and N
4
and N
6
, to produce a data evaluation window having a width
210
. The resulting data evaluation window is felt at a pair of pull-down nodes
118
and
120
at the sources of NFETs N
1
and N
2
, respectively.
During a data evaluation window at pull-down nodes
118
and
120
data propagates through D-latch
100
. At the onset of a data evaluation window (i.e., at a rising edge of C), the biasing at pull-down nodes
118
and
120
enables a pair of CMOS inverters comprising P
1
and N
1
, and P
4
and N
2
, respectively, to pass the input data through an internal data path node
104
and into a storage node
102
. From storage node
102
, the data propagates through inverter I
6
to complementary output node
112
and through inverters I
4
and I
7
to output node
114
. PFETs P
2
and P
3
suppress noise by maintaining a logic high at internal data path node
104
during non-data transfer cycles.
An ideal D-latch design provides a temporally symmetric complementary output as well as an optimized balance between performance and electrical efficiency. However, as illustrated in
FIG. 2
, the data path for Q is longer (four logic stages) than that for {overscore (Q)} (three logic stages), resulting in an unbalanced differential output. In addition to having an unbalanced output, D-latch
100
suffers a reduced power efficiency due to periodic “glitches” experienced by internal data path node
104
wherein a high-to-low transition occurs for each clock cycle even in the absence of a change in the data input. Finally, the performance of D-latch
100
in terms of transfer speed is reduced by its CMOS edge-triggering design wherein additional clock pulse generating elements N
3
, N
5
, N
4
, and N
6
are required to enable edge-triggered data propagation through the CMOS inverters in the data path.
From the foregoing, it can be appreciated that a need exists for an improved clock-triggered latch wherein the foregoing limitations of conventional latches are minimized.
SUMMARY OF THE INVENTION
An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths is disclosed herein. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
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patent: 5732036 (1998-03-01), Merritt et al.
patent: 5825224 (1998-10-01), Klass et al.
patent: 5844844 (1998-12-01), Bauer et al.
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patent: 5949266 (1999-09-01), Hinds et al.
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patent: 6060927 (2000-05-01), Lee
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patent: 6121797 (2000-09-01), Song et al.
patent: 6163192 (2000-12-01), Lee et al.
U.S. patent application No. 09/810,027, Kojima et al., filed Mar. 15, 2001.

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