Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1998-08-25
2001-06-26
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S026000, C327S264000, C327S281000
Reexamination Certificate
active
06252447
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to variable impedance power supply delay elements for use in such integrated circuit devices.
2. Description of the Prior Art
Throughout the design, test, and manufacture of integrated circuit devices, such as memory devices, there exists the need to determine circuit performance. Especially during circuit debug, speed optimization, and yield optimization, certain device parameters and corresponding critical signals must be evaluated. Such critical signals may include sense amp timing, set-up and hold times, rise and falls times, etc. Evaluation of critical signals is often accomplished by introducing delays to the critical signals to change the timing of these critical signals and then measuring how the circuit responds to such delays.
Introduction of delays is often controlled by delay elements. It is often necessary to distribute delay elements throughout the integrated circuit in order to effect a global delay for a critical signal, since the critical signal may be distributed across a chip or within repeated circuit blocks. For example, sense amp timing delays are often times found in each memory block. It is common for sense amp timing delays to be introduced to 8, 16, 32, or more circuit blocks.
There are several methods currently used in the art to introduce delays in critical signal timing. Adjustments in the delay of critical signals may be accomplished using experimental masks, but this is costly and time consuming. It could be done using a focused ion beam (FIB), but when a number of circuit blocks must be adjusted, this can be quite time consuming, prone to error, and expensive. FIB is best suited for adjusting the circuitry at a limited number of locations, rather than repetitive operations. Also, FIB does not allow for production adjustment by blowing fuses and is therefore not ideal for a production environment. Additionally, placing fuses in each delay circuit takes a great deal of layout area and is cumbersome to layout in the central block control area of the chip.
To date, methods for introducing delays to critical integrated circuit signals have required the placement of delay elements throughout the integrated circuit in distributed circuit blocks. The distribution of delay elements throughout the integrated circuit means that adjustments to these delay elements must be made at multiple locations. Methods currently used to do this, as described above, may be time consuming, prone to error, expensive, and not desirable for a production device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to globally adjust the delay of critical signals or pulse widths throughout an integrated circuit device having distributed circuit blocks.
It is therefore further an object of the present invention to adjust the delay of such signals in such a manner so as to be layout efficient.
It is therefore further an object of the present invention to adjust the delay of such signals in such a manner so as to be transparent to the normal operating mode of the integrated circuit.
Therefore, according to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.
REFERENCES:
patent: 5055706 (1991-10-01), Nakai et al.
patent: 5376848 (1994-12-01), Hanke et al.
patent: 5418756 (1995-05-01), McClure
patent: 5506534 (1996-04-01), Guo et al.
patent: 5790612 (1998-08-01), Chengson et al.
patent: 0451079 (1991-10-01), None
patent: 61-052022 (1986-03-01), None
patent: 2290328 (1990-11-01), None
patent: WO 92/16051 (1992-09-01), None
Callahan Timothy P.
Galanthay Theodore E.
Jorgenson Lisa K.
Larson Michelle
Nguyen Minh
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