Edge rate controlled output buffer circuit with controlled charg

Details Edge rate controlled output buffer circuit with controlled charg Edge rate controlled output buffer circuit with controlled charg

1991-09-27

1993-06-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, H03K 1716, H03K 190948

Patent

active

052202097

ABSTRACT:
An edge controlled output buffer circuit reduces the amplitude of power rail noise while maintaining high switching speed by controlled storage and release of charge at the output using new charge storage and discharge capacitor circuits coupled to the output. An output discharging storage capacitor (C1) is coupled to the high potential power rail (V.sub.CC). A first passgate circuit PSGT1 is coupled between the charge storage capacitor (C1) and the output (V.sub.OUT). A first control circuit (CTR1) is coupled to the control node (m2) of the first passgate circuit (PSGT1) for transient turn on of the first passgate circuit (PSGT1) when the output is still at high potential level during transition from high to low potential level at the output. A second passgate circuit (PSGT2) is coupled between the charge storage capacitor (C1) and the low potential power rail (GND). The first control circuit (CTR1) is coupled to the control node (m4) of the second passgate circuit (PSGT2) for turn on of the second passgate circuit when the output is at low potential level following the transition. The charge storage capacitor (C1) performs transient storage of discharge from output load capacitance (CL) to reduce ground bounce during a first phase of the transition. The charged capacitor C1 provides transient sourcing of counteracting current for dissipating ground undershoot energy during a second phase of the transition. Similar measures are provided on the supply side of the output buffer circuit for reducing V.sub.CC droop and overshoot without sacrificing switching speed.

REFERENCES:
patent: 4609834 (1986-09-01), Gal
patent: 4628218 (1986-12-01), Nakaizumi
patent: 4959562 (1990-09-01), Ootani
patent: 4978870 (1990-12-01), Chen et al.
patent: 5023472 (1991-06-01), Hashimoto et al.
patent: 5087837 (1992-02-01), Cline

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