Edge polysilicon buffer LOCOS isolation

Details Edge polysilicon buffer LOCOS isolation Edge polysilicon buffer LOCOS isolation

1998-08-21

2000-10-17

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

H01L 2176

Patent

active

06133118&

ABSTRACT:
The present invention discloses an isolation method for fabricating isolation regions with less bird's peak sizes in semiconductor devices. A first pad oxide layer and a silicon nitride layer are first formed on a wafer substrate. After an undercut process is performed to the first pad oxide layer and forms a cave under the silicon nitride layer, a second pad oxide layer is formed over the wafer substrate. Next, a polysilicon layer is then deposited along the profile described above. Then, an anisotropic process is used to form sidewall spacers by etching the polysilicon layer. A recessed structure is then formed to the wafer substrate by a semi-isotropic process, and follows a thermal oxidation to fabricate isolation regions composed of silicon dioxide on the surface of the wafer substrate. The silicon nitride layer and the first pad oxide layer are then removed for continuing the active region processes.

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