Edge pad architecture for semiconductor memory

Details Edge pad architecture for semiconductor memory Edge pad architecture for semiconductor memory

2008-07-29

2008-07-29

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

07405957

ABSTRACT:
A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and configured with the data path to bus data to and from the memory bank array. The data pads are further configured such that each of the data pads are located adjacent the first and second edges of the wafer. The memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer and at least one of the data pads used to bus data is located on the second edge of the wafer.

REFERENCES:
patent: 5712827 (1998-01-01), Ogihara et al.
patent: 6515505 (2003-02-01), Rees
patent: 6806582 (2004-10-01), Ahn et al.
patent: 6873563 (2005-03-01), Suwa et al.
patent: 6886070 (2005-04-01), Stafford
patent: 2001/0049766 (2001-12-01), Stafford
patent: 2003/0076702 (2003-04-01), Kyung et al.
patent: 2004/0233721 (2004-11-01), Kim et al.
patent: 2005/0130464 (2005-06-01), Grabbe
PCT International Search Report for International Application No. PCT/EP2006/012572 mailed on Jun. 12, 2007 (4 pages).

Affiliated with

Also associated with

Rating

Edge pad architecture for semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Edge pad architecture for semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Edge pad architecture for semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2809406