Edge connect wafer level stacking

Details Edge connect wafer level stacking Edge connect wafer level stacking

2007-04-13

2010-11-09

Bryant, Kiesha R (Department: 2891)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S109000, C257SE23179

Reexamination Certificate

active

07829438

ABSTRACT:
In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

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