Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2000-06-30
2002-08-20
Witle, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S706000, C257S701000, C257S709000, C438S122000
Reexamination Certificate
active
06437438
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to integrated circuits (IC). In particular, the invention relates to IC packaging.
2. Description of Related Art
Thermal management is an important problem in semiconductor manufacturing. As high performance integrated circuits (IC) such as microprocessors push for higher and higher operating frequencies, the amount of heat they generate is increased. If the heat is not quickly and adequately dissipated, the increased temperatures may affect the performance and accelerate the aging process of the IC's.
One approach to deal with heat generation is to use heat sinks to transfer or dissipate heat. A typical heat sink includes a thermal plate to be positioned in contact with the die or the core of the IC, either directly or via some thermal interface layer such as thermal grease. Although the traditional heat sink technique seems to provide some relief for thermal management, it incurs additional problems. One of these problems is the increase in electromagnetic interference (EMI) or radio frequency interference (RFI) caused by increase in eddy currents. Eddy currents are generated due to the interaction between the high switching rate of currents through the core and the thermal plate. The thermal plate acts like a radiation antenna that can generate significant radiation.
Therefore, there is a need to have a technique that can limit the eddy currents in thermal management.
SUMMARY
The present invention is a method and apparatus to limit eddy current in a thermal plate. A plate is coupled to a die of an integrated circuit for thermal dissipation. The plate has first and second pluralities of grooves comprising non-periodic lines in first and second directions, respectively. The first and second pluralities of grooves form a grid pattern.
REFERENCES:
patent: 5491301 (1996-02-01), Akiba et al.
patent: 6085833 (2000-07-01), Kimura et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Dilinh
Witle Douglas
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