Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2001-10-16
2004-06-08
Nicolas, Wesley A. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S102000, C205S103000, C205S118000, C205S123000
Reexamination Certificate
active
06746591
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electroplating processes for sub-quarter micron semiconductor devices. More particularly, the present invention relates to electroplating copper into vias of sub-quarter micron semiconductor devices.
2. Description of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines, and other features. Reliable formation of these interconnect features is critical to the success of ULSI and to the continued effort to reliably increase circuit density on individual substrates and die.
As circuit density increases, the widths of vias, contacts, and other features, as well as the width of the dielectric materials positioned therebetween, decreases to less than 250 nanometers, while the thickness of the dielectric layers themselves remains substantially constant. This results in the aspect ratios for the features, i.e., their height divided by width, increasing, often well over 4:1. However, many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), for example, are known to have difficulty filling high aspect ratio features and structures, particularly when the aspect ratio exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed toward the formation of void-free, nanometer-sized features having high aspect ratios, i.e., 4:1 or higher. Additionally, as the feature width decreases, the device electrical current generally remains constant or increases, which results in an increased current density in the feature.
Elemental aluminum (Al) and several of it's alloys have been the traditional metals used to form lines and plugs in semiconductor processing as a result of aluminum's perceived low electrical resistivity, its superior adhesion to silicon dioxide (SiO
2
), its ease of patterning, and the availability of aluminum in a relatively pure form. Tungsten and it's alloys have also been a conventional choice for line and plug formation as a result of the resistivity exhibited therefrom. However, aluminum and tungsten both have higher electrical resistivities than other more conductive metals, such as copper, for example, and further, aluminum and tungsten typically offer poor resistance to electromigration.
Copper and its alloys appear to be promising replacements for conventional aluminum and tungsten based processes, as copper generally exhibits lower resistivity than aluminum and tungsten, while also offering significantly higher electromigration resistances than aluminum and tungsten. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Additionally, copper also exhibits favorable thermal conductivity and is readily available in a relatively pure state. Therefore, copper is generally becoming a choice metal for filling sub-quarter micron high aspect ratio interconnect features on semiconductor substrates.
Aside from the desirability for using copper in semiconductor device fabrication, effective fabrication methods for depositing copper into very high aspect ratio features, such as a 4:1 or higher having 0.35 &mgr; (or less) wide vias are limited, as known deposition techniques, such as PVD and CVD, are generally not effective in completely filling these small vias in copper based systems. Therefore, in order to facilitate the use of copper in semiconductor device fabrication, electroplating processes, which have previously been limited to the fabrication of lines and/or bump solder points, are now being investigated as possible processes for filling vias and contacts on sub-quarter micron semiconductor devices.
Metal electroplating processes are generally known, and may be achieved through a variety of techniques. A typical electroplating method used to manufacture semiconductor devices generally includes using either a CVD or a PVD process to deposit a barrier layer over feature surfaces, using another CVD or PVD process to deposit a conductive metal seed layer over the barrier layer, which is preferably copper, and then electroplating a conductive metal layer over the seed layer to fill the structure/feature. Finally, the deposited layers may then be planarized, through, for example, a chemical mechanical polishing (CMP) process, to remove the overburden and reveal the properly defined and filled conductive interconnect feature.
When copper is used as the conductive material in the electroplating process, a lower resistivity is shown and destructive cross talk is generally reduced. However, the process of electroplating copper into and filling sub-quarter micron vias through conventional electroplating processes has been shown to be unsuccessful, as the limited dimensions of sub-quarter micron vias generally does not allow for sufficient electrolyte flow into and out of the vias to support sustained electroplating. For example, when an electroplating process is used to fill a sub-quarter micron via, the surface containing the via is generally exposed to a flow of electrolyte having the plating material therein. A constant electrical bias is then applied between the electrolyte and the surface to be plated (seed layer), which acts to bias or pull the plating material (ions) from the electrolyte and plate/deposit the ions on the plating surface. However, the plating process depletes plating ions from the electrolyte, and therefore, it is generally necessary to supply fresh electrolyte to the plating surface in order to provide a continual supply of ions to be plated. The supply of fresh electrolyte to flat surfaces to be plated is easily accomplished. However, when it comes to sub-quarter micron vias, it is generally not possible to flow electrolyte into the ion depleted regions of vias as a result of the limited dimensions of the via itself. Therefore, the plating ions must generally diffuse from areas of high ion concentration within the electrolyte outside the vias into areas of lower ion concentration inside the vias in order for the via to be plated or filled. The plating ions are generally caused to diffuse into the vias by the constant electrical plating bias applied between the substrate and the electrolyte, which operates to urge plating ions to diffuse through the electrolyte to areas of lower ion concentration within the electrolyte. Dynamic fluid diffusion principles are the general cause for the diffusion of the plating ions through the electrolyte to areas of low ion concentration. However, fluid diffusion of plating ions from one concentration to another in conventional plating systems is extremely slow and generally impracticable for semiconductor plating processes. Additionally, the diffusion of plating ions as a result of the electrical plating bias is known to be a slow process, as well as potentially causing closure of the vias prior to filling.
Therefore, in view of the deficiencies of conventional plating apparatuses and processes for sub-quarter micron vias, there is a need for a plating apparatus and method capable of accelerating diffusion of plating ions into vias of sub-quarter micron devices. Further, there is a need for a plating apparatus and method capable of accelerating diffusion of plating ions into vias while avoiding closure prior to completely filling the via.
SUMMARY OF THE INVENTION
Embodiments of the invention generally provide a processing cell for an electrochemical deposition system. The processing cell includes a head assembly configured to support a wafer, the head assembly including a cathode, and an electrolyte container configured to hold a fluid electrolyte therein and having an anode disposed within the container. The processing cell further includes a power supply in
Dixit Girish
He Renren
Zheng Bo
Applied Materials Inc.
Moser Patterson & Sheridan
Nicolas Wesley A.
LandOfFree
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