ECL to TTL translator with power supply noise suppression

Details ECL to TTL translator with power supply noise suppression ECL to TTL translator with power supply noise suppression

1994-03-31

1995-07-11

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326126, H03K 19018

Patent

active

054324661

ABSTRACT:
A translator circuit (21) converts an ECL logic level to a TTL logic level. The translator circuit (21) operates at high speeds, rejects power supply noise, and does not use Schottky diodes for preventing transistors from saturating. The translator circuit comprises a differential input stage (22), a level shift stage (23), a differential stage (24), and an output stage (25). The differential input stage (22) is responsive to an ECL signal and provides a differential output signal. The level shift stage (23) level shifts the differential output signal of the differential input stage a predetermined DC voltage. The differential stage (24) is responsive to the level shift stage (23) and generates first and second output signals. The differential stage (24) rejects power supply noise coupled from the level shift stage (23). The output stage (25) is responsive to the first and second output signals of the differential stage (24) and converts the first and second signals to a single ended TTL signal corresponding to the logic level of the ECL signal.

REFERENCES:
patent: 4401901 (1983-08-01), Ochi
patent: 4647799 (1987-03-01), Hsu et al.
patent: 4877977 (1989-10-01), Kokado
patent: 4939393 (1990-07-01), Petty
patent: 5013941 (1991-05-01), Jansson
patent: 5025179 (1991-06-01), Freitas

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