ECL to CMOS level translator using delayed feedback for high spe

Details ECL to CMOS level translator using delayed feedback for high spe ECL to CMOS level translator using delayed feedback for high spe

1996-06-18

1998-03-17

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326 68, H03K 190185

Patent

active

057291560

ABSTRACT:
A voltage level translator for converting a small-signal differential ECL input signal into a full rail, single-ended CMOS output signal, wherein the difference in current generated by a pair of P-channel transistors as a result in a transitioning of the ECL signal is "mirrored" by a pair of N-channel output transistors, causing the CMOS output voltage to transition, the delay in transitioning of the output transistors being minimized through the use of delayed feedback.

REFERENCES:
patent: 5136190 (1992-08-01), Chern et al.
patent: 5357149 (1994-10-01), Kimura
patent: 5384737 (1995-01-01), Childs et al.
patent: 5467313 (1995-11-01), Jung et al.
patent: 5606268 (1997-02-01), Van Brunt

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