ECL to CMOS level converter

Electronic digital logic circuitry – Interface – Logic level shifting

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326110, 327 51, H03K 90175

Patent

active

053828453

ABSTRACT:
It is an object of the present invention to provide an amplifier circuit for amplifying the voltage amplitude of a small amplitude signal to the CMOS level which operates at a high speed with low power dissipation while assuring high gain. PMOS FETs M.sub.11, M.sub.16 for pulling up the output are of the source-driving type and receive signals V.sub.IN1, V.sub.IN1i, respectively, and NMOS FETs M.sub.12, M.sub.17 for pulling down the output are of the gate-driving type and receive level shifted signals V.sub.IN2, V.sub.IN2i, respectively. In the circuit of the present invention, constant voltages for reference are set by diodes D.sub.13, D.sub.14, and bipolar transistors are connected as transistors for driving an output portion of the amplifier circuit. The performance of the amplifier circuit of the invention when it is used as a sensing amplifier to drive a TTL output is improved such that amplification gain is as high as two to five times and the response time/consumed current product is as low as one fifth to one tenth as compared with a conventional amplifier circuit.

REFERENCES:
patent: 5039886 (1991-08-01), Nakamura et al.
patent: 5070261 (1991-12-01), Teneyck
patent: 5075579 (1991-12-01), Ueno
patent: 5214328 (1993-05-01), Ohi
M. Suzuki et al., "High-Speed SRAMs", ISSCC Digest of Technical Papers, 1989, pp. 32-33.
Stephen Flannagan et al., "Static RAMs", ISSCC Digest of Technical Papers, 1990, pp. 134-135.

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