ECL test access port with low power control

Details ECL test access port with low power control ECL test access port with low power control

1993-04-02

1995-01-03

Voeltz, Emanuel T.

Excavating

3241581, 371 221, 371 222, 326 16, 326126, 326127, 327199, G06F 1100

Patent

active

053793021

ABSTRACT:
An integrated circuit device ECL test access port (TAP) is constructed for low static current requirements and low power consumption when the TAP is inactive. The ECL test access port may conform with IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. An SCS logic circuit (50) is incorporated in the TAP controller coupled to the flip-flops (32,34,36,38) of the TAP controller n state finite machine for generating a current sink switch control signal (SCS) according to the state of the TAP controller. A current sink switch circuit (24) is coupled to respective current sinks of ECL gates incorporated in the boundary scan register (BSR/TDR1), design specific TAP data registers (DS/TDRs), TAP instruction register (TIR), and device identification register (DIR/TDR3). The current sink switch circuit (24) has an input coupled to the SCS logic circuit (50) to receive the current sink switch control signal (SCS). The current sink switch circuit is constructed to turn off the respective current sinks (Q4/R5, Q5/R6, Q6/R7) of the selected TAP registers in response to an SCS signal having a first logic value to reduce power dissipation when the TAP controller is in the inactive test logic reset (TLR) state. The current sink switch circuit turns on the respective current sinks of the selected TAP registers in response to an SCS signal having a second logic value when the test controller is in an active test mode state. The SCS logic circuit incorporates appropriate decoder or logic gates (40,52) and reset signal (RESET*) to filter out glitches and spikes and provide a clean SCS signal for holding on or off the respective current sinks of the ECL logic gates of the selected TAP registers.

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IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Computer Society, (IEEE Standard 1149.1) IEEE, New York 1990.

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