ECL output buffer with a MOS transistor used for tristate enable

Details ECL output buffer with a MOS transistor used for tristate enable ECL output buffer with a MOS transistor used for tristate enable

1994-03-21

1995-07-18

Westin, Edward P.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326 84, 326109, H03K 19086

Patent

active

054345170

ABSTRACT:
An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

REFERENCES:
patent: 4678943 (1987-07-01), Uragami et al.
patent: 4980579 (1990-12-01), McDonald et al.
patent: 4999519 (1991-03-01), Kitsukawa et al.
patent: 5101123 (1992-03-01), Ten Eyck
patent: 5172015 (1992-12-01), Barre
patent: 5300832 (1994-04-01), Rogers

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