ECL high speed semiconductor memory and method of accessing stor

Details ECL high speed semiconductor memory and method of accessing stor ECL high speed semiconductor memory and method of accessing stor

1987-06-02

1989-08-15

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365177, 365179, 365154, 365156, G11C 1134, G11C 1100

Patent

active

048581836

ABSTRACT:
A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to read data therefrom. Data is accessed through a bipolar transistor (120) for output to an ECL sense amp. The column select operation is provided by an ECL decoder (50) to select both the Read and the Write operation. The Write operation is provided with emitter coupled logic by pulling up one of the storage nodes in the CMOS latch (70) with a low source impedance PNP transistor (122). Selection is provided by varying the Word Line between two voltages through a low source impedance transistor (78) with the voltages being ECL compatible.

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A 4 nsec 4Kx1bit Two-Port BiCMOS SRAM, by T. S. Yang, M. A. Horozitz and B. A. Wooley, Proc. 1988 Custom Integrated Circuits Conference, May 1988.

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