ECL/CMOS memory cell with separate read and write bit lines

Details ECL/CMOS memory cell with separate read and write bit lines ECL/CMOS memory cell with separate read and write bit lines

1986-06-19

1987-10-20

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365175, G11C 1140

Patent

active

047018836

ABSTRACT:
A CMOS memory cell is provided having separate read and write bit lines and coupling devices associated therewith which provide improved read and write times for the cell. The separate read line is coupled to the cell via a bipolar transistor which supplies increased drive current to the read bit line thereby decreasing the read time. The separate write line is coupled to the cell via a low impedance diode which reduces the write time.

REFERENCES:
patent: 4630238 (1986-12-01), Arakawa

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