Echo clock on memory system having wait information

Details Echo clock on memory system having wait information Echo clock on memory system having wait information

2006-02-07

2006-02-07

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S233100

Reexamination Certificate

active

06996016

ABSTRACT:
A method and a circuit configuration for implementing a double data rate feature in a memory device capable of operating in a variable latency mode. The memory device may utilize a WAIT_DQS signal that combines functionality of a WAIT signal indicating when valid data is present on a data bus in Read cycle and the memory is ready to accept data in Write cycle, and a data strobe (DQS) signal.

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