ECC flag for testing on-chip error correction circuit

Details ECC flag for testing on-chip error correction circuit ECC flag for testing on-chip error correction circuit

2008-05-13

2008-05-13

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

11132562

ABSTRACT:
The present invention includes an error correction circuit with a data memory, a control circuit, a parity memory, and a recorder. The data memory is configured to receive and store a set of data. The control circuit is configured to receive the set of data and to generate parity bits in response thereto. A parity memory is coupled to the control circuit and configured to receive and hold parity bits. The control circuit is further configured to combine the parity bits from the parity memory with the set of data from the data memory to determine whether an error occurred in the set of data. The recorder is coupled to the control circuit and configured to record an indication of whether an error occurred in the set of data.

REFERENCES:
patent: 6543029 (2003-04-01), Sandorfi
patent: 6754858 (2004-06-01), Borkenhagen et al.
patent: 6792567 (2004-09-01), Laurent
patent: 6851081 (2005-02-01), Yamamoto
patent: 2005/0044467 (2005-02-01), Leung et al.
patent: 2006/0156192 (2006-07-01), Nakamura et al.
University of New Brunswick, “Error Correction and the Hamming Code, EE4253 Digital Communications,” pp. 1-4, (Apr. 2, 2002) <http://www.ee.unb.ca/tervo/ee4253/hamming.htm>.

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