ECC coding for high speed implementation

Details ECC coding for high speed implementation ECC coding for high speed implementation

2005-11-21

2008-11-04

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C714S764000, C714S002000, C714S006130, C714S042000, C714S048000, C714S718000, C714S719000, C714S746000, C714S758000, C714S799000, C714S800000, C714S802000, C714S804000, C714S807000, C714S818000

Reexamination Certificate

active

07447948

ABSTRACT:
Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

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